User contributions for Ulfalizer
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22 November 2015
- 13:5713:57, 22 November 2015 diff hist −23 PPU registers Rewrite confusing sentence re. when the sprite 0 hit flag is cleared
14 June 2015
- 12:1812:18, 14 June 2015 diff hist +257 Visual circuit tutorial Undo revision 11163 by Ulfalizer (talk)
9 June 2015
- 11:2911:29, 9 June 2015 diff hist −257 m Visual circuit tutorial Nit.
18 May 2015
- 03:5303:53, 18 May 2015 diff hist −3 m Visual circuit tutorial hints at -> shows
- 03:3603:36, 18 May 2015 diff hist +65 Visual circuit tutorial There's transistors on the power sources too though
- 03:3303:33, 18 May 2015 diff hist +299 Visual circuit tutorial Clarify that the metal + poly overlap in the NOR example does not form transistors
16 May 2015
- 22:0722:07, 16 May 2015 diff hist −1 Visual circuit tutorial Grammar nit
- 21:4821:48, 16 May 2015 diff hist +11 Visual circuit tutorial Hint that a refresh might be similar to a real access
- 20:4920:49, 16 May 2015 diff hist +10 Visual circuit tutorial Have "latch" in the title of the latch section
- 19:3019:30, 16 May 2015 diff hist +2 m Visual circuit tutorial Nits
- 19:0019:00, 16 May 2015 diff hist −2 Visual circuit tutorial ...some more
- 18:5818:58, 16 May 2015 diff hist −2 Visual circuit tutorial De-parenthesize
- 18:5518:55, 16 May 2015 diff hist −21 Visual circuit tutorial "Which we would label" is redundant. '/' was already explained.
- 18:4718:47, 16 May 2015 diff hist +9 Visual circuit tutorial Small clocked latches clarification
- 18:4118:41, 16 May 2015 diff hist −112 Visual circuit tutorial The explanation for the NORiness of the latch is redundant given the image
- 18:3018:30, 16 May 2015 diff hist +1 Visual circuit tutorial Replace -- with en-dash
- 18:2918:29, 16 May 2015 diff hist −5 m Visual circuit tutorial De-will one more place
- 18:2418:24, 16 May 2015 diff hist 0 Visual circuit tutorial Nit
- 18:2218:22, 16 May 2015 diff hist +34 Visual circuit tutorial Was probably a good thing to explain why there might be a short
- 18:1618:16, 16 May 2015 diff hist −103 Visual circuit tutorial Simplify some more
- 18:0218:02, 16 May 2015 diff hist −30 m Visual circuit tutorial Language simplification nits
- 17:5017:50, 16 May 2015 diff hist −156 Visual circuit tutorial Remove potentially confusing note on S/R vs copied-into latches
- 17:4517:45, 16 May 2015 diff hist −1 Visual circuit tutorial Separate out power source + transistor example into its own section
- 17:4117:41, 16 May 2015 diff hist +11 Visual circuit tutorial Slight clean-up in power source + transistor examples
- 17:3317:33, 16 May 2015 diff hist +3 m Visual circuit tutorial s/unimportant/less important/
- 17:0717:07, 16 May 2015 diff hist −16 m Visual circuit tutorial Nits
- 16:5916:59, 16 May 2015 diff hist +2 m Visual circuit tutorial Use consistent hyphen style
- 16:5616:56, 16 May 2015 diff hist +4 Visual circuit tutorial Emphasize a 'not'
- 16:5516:55, 16 May 2015 diff hist +10 Visual circuit tutorial Clean up 'Wire capacitance as storage' section
- 16:4116:41, 16 May 2015 diff hist +33 Visual circuit tutorial Point out the power source in the NOR section
- 16:3816:38, 16 May 2015 diff hist +13 Visual circuit tutorial Simplify inverter example + nits
14 May 2015
- 17:4417:44, 14 May 2015 diff hist +978 INES Mapper 028 Add visualization that might be helpful.
- 17:1517:15, 14 May 2015 diff hist +128 INES Mapper 028 Clarify how R:$01 works in 32K mode. The old version could be misunderstood as right-shifting it to get a 32K bank number.
- 07:4507:45, 14 May 2015 diff hist +8 INES Mapper 028 CHR bank is specified in R:$00 and "I" is confusing without explaining the mnemonic
13 May 2015
- 14:3514:35, 13 May 2015 diff hist −1 MMC2 Mapper number should be 9 and not 10 in table. Prolly a copy-paste error from MMC4.
- 13:0413:04, 13 May 2015 diff hist +13 MMC2 "Left" and "right" are confusing if you haven't played much with pattern table viewers
- 13:0213:02, 13 May 2015 diff hist +6 MMC4 "Left" is confusing if you haven't played much with pattern table viewers
11 May 2015
- 03:3303:33, 11 May 2015 diff hist −16 Tricky-to-emulate games No edit summary
- 01:0401:04, 11 May 2015 diff hist −3 Tricky-to-emulate games No edit summary
- 01:0301:03, 11 May 2015 diff hist −2 Tricky-to-emulate games No edit summary
- 01:0201:02, 11 May 2015 diff hist +348 Tricky-to-emulate games Battletoads & Double Dragon dislikes WRAM
18 January 2015
- 22:1522:15, 18 January 2015 diff hist −26 PPU power up state Simplify explanation a bit more.
- 22:1222:12, 18 January 2015 diff hist −27 PPU power up state Reformulate and reorganize a bit for readability.
- 22:0122:01, 18 January 2015 diff hist −313 PPU power up state Remove bullet point. Just noticed that the explanation is already given further down.
- 21:5621:56, 18 January 2015 diff hist −20 m PPU power up state Slight reformulation.
- 21:5521:55, 18 January 2015 diff hist +333 PPU power up state Explain why writes to certain registers are ignored after reset.
16 September 2014
- 11:4711:47, 16 September 2014 diff hist −2 Visual circuit tutorial State early that we're dealing with NMOS
14 February 2014
- 15:2715:27, 14 February 2014 diff hist +9 m Visual circuit tutorial No edit summary
- 15:2615:26, 14 February 2014 diff hist +67 m Visual circuit tutorial Slight reformulation
- 15:2015:20, 14 February 2014 diff hist +4 m Visual circuit tutorial No edit summary
- 15:1715:17, 14 February 2014 diff hist −1 m Visual circuit tutorial No edit summary
- 15:1715:17, 14 February 2014 diff hist +246 Visual circuit tutorial Introduce the / notation the first time it appears
18 January 2014
- 05:1805:18, 18 January 2014 diff hist −96 m Visual circuit tutorial Misc. minor cleanup
- 05:1305:13, 18 January 2014 diff hist 0 m Visual circuit tutorial No edit summary
12 December 2013
- 06:5706:57, 12 December 2013 diff hist +20 m File talk:Ntsc timing.png No edit summary current
- 06:5606:56, 12 December 2013 diff hist +346 File talk:Ntsc timing.png Skipped tick on odd frames with rendering enabled
4 December 2013
- 17:3917:39, 4 December 2013 diff hist +5 m Visual circuit tutorial No edit summary
- 10:2110:21, 4 December 2013 diff hist −26 Visual circuit tutorial Rephrase to avoid "electrically common" as it gets confusing with the section that follows
- 09:1209:12, 4 December 2013 diff hist 0 m Visual circuit tutorial No edit summary
- 09:0709:07, 4 December 2013 diff hist +1,546 Visual circuit tutorial Add examples to introductory sections and remove forum link
4 October 2013
- 14:4114:41, 4 October 2013 diff hist +203 INES Mapper 005 Bandit Kings of Ancient China writes PRG RAM through the ROM area
- 11:0811:08, 4 October 2013 diff hist +166 INES Mapper 005 Clarify that split screen uses absolute screen positions within the split region
12 September 2013
- 23:0123:01, 12 September 2013 diff hist +259 CPU interrupts Add short intro
10 September 2013
- 12:1612:16, 10 September 2013 diff hist +74 APU The triangle's linear counter does not influence status in $4015 reads (confirmed in Visual 2A03 circuitry)
9 September 2013
- 13:3013:30, 9 September 2013 diff hist +1 m APU DMC No edit summary
- 13:1613:16, 9 September 2013 diff hist +473 APU DMC Clarify that the bits-remaining counter is always ticking
29 August 2013
- 11:3911:39, 29 August 2013 diff hist +1 m CPU interrupts No edit summary
- 11:3611:36, 29 August 2013 diff hist +102 CPU interrupts Try to be clearer about the output from the level detector
- 11:3311:33, 29 August 2013 diff hist 0 m CPU interrupts No edit summary
- 11:3211:32, 29 August 2013 diff hist +136 CPU interrupts Rephrase detailed behavior in terms of edge and level detectors and fix CLI inaccuracy (the flag really changes during the "third" cycle, overlapping the opcode fetch)
26 August 2013
- 07:1907:19, 26 August 2013 diff hist −6 m CPU interrupts No edit summary
- 07:1607:16, 26 August 2013 diff hist +143 CPU interrupts All two-cycle instructions poll interrupts at the end of the first cycle (as a side note, this is why the branch instructions do too, since they can be two-cycle)
- 06:5306:53, 26 August 2013 diff hist +201 CPU interrupts NMI priority over IRQ
- 06:2706:27, 26 August 2013 diff hist +346 CPU interrupts Give possible explanation for why interrupts are sometimes said to be polled during the final cycle
- 06:1106:11, 26 August 2013 diff hist +1 m CPU interrupts No edit summary
- 06:1006:10, 26 August 2013 diff hist +148 CPU interrupts Be clearer about how IRQ and NMI are similar
- 06:0306:03, 26 August 2013 diff hist +185 CPU interrupts A reset is basically just another interrupt type
- 05:5605:56, 26 August 2013 diff hist +16 m CPU interrupts No edit summary
- 05:5405:54, 26 August 2013 diff hist −7 CPU interrupts s/during before/before/
- 05:5305:53, 26 August 2013 diff hist −5 CPU interrupts Branch instructions poll interrupts just before the second cycle (like all two-cycle instructions do)
- 05:4905:49, 26 August 2013 diff hist +70 CPU interrupts Interrupts are polled right before the PCH fixup cycle for branches. Looks like the interrupt hijacking timing was already correct.
- 05:3805:38, 26 August 2013 diff hist −56 CPU interrupts Interrupts are actually polled at the end of the second-to-last cycle (verified in Visual 6502, and doing it like that makes blargg's cpu_interrupts_v2 pass) (more changes coming)
20 August 2013
- 21:3721:37, 20 August 2013 diff hist +377 User:Ulfalizer Read/write timing current
- 05:4105:41, 20 August 2013 diff hist +80 Mapper Make Disch's intro doc easier to find
19 August 2013
- 03:1603:16, 19 August 2013 diff hist +112 Talk:INES Mapper 232 No edit summary current
16 August 2013
- 02:3502:35, 16 August 2013 diff hist +29 Arpeggio Needs moar arpeggio
15 August 2013
- 09:0409:04, 15 August 2013 diff hist +45 APU Frame Counter The write delay was off by one CPU cycle too. Perhaps that compensated. (Derived from Visual 2A03.)
- 08:4408:44, 15 August 2013 diff hist +118 APU Sample restarting is delayed if the last sample byte of a previous sample is playing (rainwarrior)
- 08:3808:38, 15 August 2013 diff hist +99 APU Frame Counter The quarter and half frame signals are generated with a delay of one CPU cycle (see talk page)
13 August 2013
- 14:2814:28, 13 August 2013 diff hist +1,133 Talk:APU Frame Counter Further confirmation that ticks might be off by .5
- 11:5011:50, 13 August 2013 diff hist +510 Talk:APU Frame Counter Some times off by .5?
6 August 2013
- 17:2517:25, 6 August 2013 diff hist 0 File:Ntsc timing.png Ulfalizer uploaded a new version of "File:Ntsc timing.png": Specify where background shift registers shift and where they are reloaded at the end of the scanline.
- 17:2317:23, 6 August 2013 diff hist 0 File:Ppu.svg Ulfalizer uploaded a new version of "File:Ppu.svg": Some of the text in the notes didn't render for some reason.
- 17:1717:17, 6 August 2013 diff hist 0 File:Ppu.svg Ulfalizer uploaded a new version of "File:Ppu.svg": Specify where background shift registers shift and where they are reloaded at the end of the scanline.
22 July 2013
- 02:1802:18, 22 July 2013 diff hist +121 Visual circuit tutorial Clarify that the left transistor in the inverter example is just a resistor
- 02:0302:03, 22 July 2013 diff hist +273 Visual circuit tutorial Add temporary link to hopefully un-confusing thread
19 July 2013
- 19:4719:47, 19 July 2013 diff hist +121 PPU rendering Specify where the flag and X position loading happens during sprite loading (derived from Visual 2C02)
17 July 2013
- 20:3920:39, 17 July 2013 diff hist +90 PPU registers Probably best to just ignore writes to $2004 during rendering for emulation
- 20:3620:36, 17 July 2013 diff hist +1 m PPU registers No edit summary
- 20:3520:35, 17 July 2013 diff hist +109 PPU registers Sprite evaluation status might affect the glitchy OAMADDR increment when accessing OAMDATA during rendering
