User contributions for Ulfalizer
From NESdev Wiki
Jump to navigationJump to search
22 November 2015
- 13:5713:57, 22 November 2015 diff hist −23 PPU registers Rewrite confusing sentence re. when the sprite 0 hit flag is cleared
14 June 2015
- 12:1812:18, 14 June 2015 diff hist +257 Visual circuit tutorial Undo revision 11163 by Ulfalizer (talk)
9 June 2015
- 11:2911:29, 9 June 2015 diff hist −257 m Visual circuit tutorial Nit.
18 May 2015
- 03:5303:53, 18 May 2015 diff hist −3 m Visual circuit tutorial hints at -> shows
- 03:3603:36, 18 May 2015 diff hist +65 Visual circuit tutorial There's transistors on the power sources too though
- 03:3303:33, 18 May 2015 diff hist +299 Visual circuit tutorial Clarify that the metal + poly overlap in the NOR example does not form transistors
16 May 2015
- 22:0722:07, 16 May 2015 diff hist −1 Visual circuit tutorial Grammar nit
- 21:4821:48, 16 May 2015 diff hist +11 Visual circuit tutorial Hint that a refresh might be similar to a real access
- 20:4920:49, 16 May 2015 diff hist +10 Visual circuit tutorial Have "latch" in the title of the latch section
- 19:3019:30, 16 May 2015 diff hist +2 m Visual circuit tutorial Nits
- 19:0019:00, 16 May 2015 diff hist −2 Visual circuit tutorial ...some more
- 18:5818:58, 16 May 2015 diff hist −2 Visual circuit tutorial De-parenthesize
- 18:5518:55, 16 May 2015 diff hist −21 Visual circuit tutorial "Which we would label" is redundant. '/' was already explained.
- 18:4718:47, 16 May 2015 diff hist +9 Visual circuit tutorial Small clocked latches clarification
- 18:4118:41, 16 May 2015 diff hist −112 Visual circuit tutorial The explanation for the NORiness of the latch is redundant given the image
- 18:3018:30, 16 May 2015 diff hist +1 Visual circuit tutorial Replace -- with en-dash
- 18:2918:29, 16 May 2015 diff hist −5 m Visual circuit tutorial De-will one more place
- 18:2418:24, 16 May 2015 diff hist 0 Visual circuit tutorial Nit
- 18:2218:22, 16 May 2015 diff hist +34 Visual circuit tutorial Was probably a good thing to explain why there might be a short
- 18:1618:16, 16 May 2015 diff hist −103 Visual circuit tutorial Simplify some more
- 18:0218:02, 16 May 2015 diff hist −30 m Visual circuit tutorial Language simplification nits
- 17:5017:50, 16 May 2015 diff hist −156 Visual circuit tutorial Remove potentially confusing note on S/R vs copied-into latches
- 17:4517:45, 16 May 2015 diff hist −1 Visual circuit tutorial Separate out power source + transistor example into its own section
- 17:4117:41, 16 May 2015 diff hist +11 Visual circuit tutorial Slight clean-up in power source + transistor examples
- 17:3317:33, 16 May 2015 diff hist +3 m Visual circuit tutorial s/unimportant/less important/
- 17:0717:07, 16 May 2015 diff hist −16 m Visual circuit tutorial Nits
- 16:5916:59, 16 May 2015 diff hist +2 m Visual circuit tutorial Use consistent hyphen style
- 16:5616:56, 16 May 2015 diff hist +4 Visual circuit tutorial Emphasize a 'not'
- 16:5516:55, 16 May 2015 diff hist +10 Visual circuit tutorial Clean up 'Wire capacitance as storage' section
- 16:4116:41, 16 May 2015 diff hist +33 Visual circuit tutorial Point out the power source in the NOR section
- 16:3816:38, 16 May 2015 diff hist +13 Visual circuit tutorial Simplify inverter example + nits
14 May 2015
- 17:4417:44, 14 May 2015 diff hist +978 INES Mapper 028 Add visualization that might be helpful.
- 17:1517:15, 14 May 2015 diff hist +128 INES Mapper 028 Clarify how R:$01 works in 32K mode. The old version could be misunderstood as right-shifting it to get a 32K bank number.
- 07:4507:45, 14 May 2015 diff hist +8 INES Mapper 028 CHR bank is specified in R:$00 and "I" is confusing without explaining the mnemonic
13 May 2015
- 14:3514:35, 13 May 2015 diff hist −1 MMC2 Mapper number should be 9 and not 10 in table. Prolly a copy-paste error from MMC4.
- 13:0413:04, 13 May 2015 diff hist +13 MMC2 "Left" and "right" are confusing if you haven't played much with pattern table viewers
- 13:0213:02, 13 May 2015 diff hist +6 MMC4 "Left" is confusing if you haven't played much with pattern table viewers
11 May 2015
- 03:3303:33, 11 May 2015 diff hist −16 Tricky-to-emulate games No edit summary
- 01:0401:04, 11 May 2015 diff hist −3 Tricky-to-emulate games No edit summary
- 01:0301:03, 11 May 2015 diff hist −2 Tricky-to-emulate games No edit summary
- 01:0201:02, 11 May 2015 diff hist +348 Tricky-to-emulate games Battletoads & Double Dragon dislikes WRAM
18 January 2015
- 22:1522:15, 18 January 2015 diff hist −26 PPU power up state Simplify explanation a bit more.
- 22:1222:12, 18 January 2015 diff hist −27 PPU power up state Reformulate and reorganize a bit for readability.
- 22:0122:01, 18 January 2015 diff hist −313 PPU power up state Remove bullet point. Just noticed that the explanation is already given further down.
- 21:5621:56, 18 January 2015 diff hist −20 m PPU power up state Slight reformulation.
- 21:5521:55, 18 January 2015 diff hist +333 PPU power up state Explain why writes to certain registers are ignored after reset.
16 September 2014
- 11:4711:47, 16 September 2014 diff hist −2 Visual circuit tutorial State early that we're dealing with NMOS
14 February 2014
- 15:2715:27, 14 February 2014 diff hist +9 m Visual circuit tutorial No edit summary
- 15:2615:26, 14 February 2014 diff hist +67 m Visual circuit tutorial Slight reformulation
- 15:2015:20, 14 February 2014 diff hist +4 m Visual circuit tutorial No edit summary
- 15:1715:17, 14 February 2014 diff hist −1 m Visual circuit tutorial No edit summary
- 15:1715:17, 14 February 2014 diff hist +246 Visual circuit tutorial Introduce the / notation the first time it appears
18 January 2014
- 05:1805:18, 18 January 2014 diff hist −96 m Visual circuit tutorial Misc. minor cleanup
- 05:1305:13, 18 January 2014 diff hist 0 m Visual circuit tutorial No edit summary
12 December 2013
- 06:5706:57, 12 December 2013 diff hist +20 m File talk:Ntsc timing.png No edit summary current
- 06:5606:56, 12 December 2013 diff hist +346 File talk:Ntsc timing.png Skipped tick on odd frames with rendering enabled
4 December 2013
- 17:3917:39, 4 December 2013 diff hist +5 m Visual circuit tutorial No edit summary
- 10:2110:21, 4 December 2013 diff hist −26 Visual circuit tutorial Rephrase to avoid "electrically common" as it gets confusing with the section that follows
- 09:1209:12, 4 December 2013 diff hist 0 m Visual circuit tutorial No edit summary
- 09:0709:07, 4 December 2013 diff hist +1,546 Visual circuit tutorial Add examples to introductory sections and remove forum link
4 October 2013
- 14:4114:41, 4 October 2013 diff hist +203 INES Mapper 005 Bandit Kings of Ancient China writes PRG RAM through the ROM area
- 11:0811:08, 4 October 2013 diff hist +166 INES Mapper 005 Clarify that split screen uses absolute screen positions within the split region
12 September 2013
- 23:0123:01, 12 September 2013 diff hist +259 CPU interrupts Add short intro
10 September 2013
- 12:1612:16, 10 September 2013 diff hist +74 APU The triangle's linear counter does not influence status in $4015 reads (confirmed in Visual 2A03 circuitry)
9 September 2013
- 13:3013:30, 9 September 2013 diff hist +1 m APU DMC No edit summary
- 13:1613:16, 9 September 2013 diff hist +473 APU DMC Clarify that the bits-remaining counter is always ticking
29 August 2013
- 11:3911:39, 29 August 2013 diff hist +1 m CPU interrupts No edit summary
- 11:3611:36, 29 August 2013 diff hist +102 CPU interrupts Try to be clearer about the output from the level detector
- 11:3311:33, 29 August 2013 diff hist 0 m CPU interrupts No edit summary
- 11:3211:32, 29 August 2013 diff hist +136 CPU interrupts Rephrase detailed behavior in terms of edge and level detectors and fix CLI inaccuracy (the flag really changes during the "third" cycle, overlapping the opcode fetch)
26 August 2013
- 07:1907:19, 26 August 2013 diff hist −6 m CPU interrupts No edit summary
- 07:1607:16, 26 August 2013 diff hist +143 CPU interrupts All two-cycle instructions poll interrupts at the end of the first cycle (as a side note, this is why the branch instructions do too, since they can be two-cycle)
- 06:5306:53, 26 August 2013 diff hist +201 CPU interrupts NMI priority over IRQ
- 06:2706:27, 26 August 2013 diff hist +346 CPU interrupts Give possible explanation for why interrupts are sometimes said to be polled during the final cycle
- 06:1106:11, 26 August 2013 diff hist +1 m CPU interrupts No edit summary
- 06:1006:10, 26 August 2013 diff hist +148 CPU interrupts Be clearer about how IRQ and NMI are similar
- 06:0306:03, 26 August 2013 diff hist +185 CPU interrupts A reset is basically just another interrupt type
- 05:5605:56, 26 August 2013 diff hist +16 m CPU interrupts No edit summary
- 05:5405:54, 26 August 2013 diff hist −7 CPU interrupts s/during before/before/
- 05:5305:53, 26 August 2013 diff hist −5 CPU interrupts Branch instructions poll interrupts just before the second cycle (like all two-cycle instructions do)
- 05:4905:49, 26 August 2013 diff hist +70 CPU interrupts Interrupts are polled right before the PCH fixup cycle for branches. Looks like the interrupt hijacking timing was already correct.
- 05:3805:38, 26 August 2013 diff hist −56 CPU interrupts Interrupts are actually polled at the end of the second-to-last cycle (verified in Visual 6502, and doing it like that makes blargg's cpu_interrupts_v2 pass) (more changes coming)
20 August 2013
- 21:3721:37, 20 August 2013 diff hist +377 User:Ulfalizer Read/write timing current
- 05:4105:41, 20 August 2013 diff hist +80 Mapper Make Disch's intro doc easier to find
19 August 2013
- 03:1603:16, 19 August 2013 diff hist +112 Talk:INES Mapper 232 No edit summary current
16 August 2013
- 02:3502:35, 16 August 2013 diff hist +29 Arpeggio Needs moar arpeggio
15 August 2013
- 09:0409:04, 15 August 2013 diff hist +45 APU Frame Counter The write delay was off by one CPU cycle too. Perhaps that compensated. (Derived from Visual 2A03.)
- 08:4408:44, 15 August 2013 diff hist +118 APU Sample restarting is delayed if the last sample byte of a previous sample is playing (rainwarrior)
- 08:3808:38, 15 August 2013 diff hist +99 APU Frame Counter The quarter and half frame signals are generated with a delay of one CPU cycle (see talk page)
13 August 2013
- 14:2814:28, 13 August 2013 diff hist +1,133 Talk:APU Frame Counter Further confirmation that ticks might be off by .5
- 11:5011:50, 13 August 2013 diff hist +510 Talk:APU Frame Counter Some times off by .5?
6 August 2013
- 17:2517:25, 6 August 2013 diff hist 0 File:Ntsc timing.png Ulfalizer uploaded a new version of "File:Ntsc timing.png": Specify where background shift registers shift and where they are reloaded at the end of the scanline.
- 17:2317:23, 6 August 2013 diff hist 0 File:Ppu.svg Ulfalizer uploaded a new version of "File:Ppu.svg": Some of the text in the notes didn't render for some reason.
- 17:1717:17, 6 August 2013 diff hist 0 File:Ppu.svg Ulfalizer uploaded a new version of "File:Ppu.svg": Specify where background shift registers shift and where they are reloaded at the end of the scanline.
22 July 2013
- 02:1802:18, 22 July 2013 diff hist +121 Visual circuit tutorial Clarify that the left transistor in the inverter example is just a resistor
- 02:0302:03, 22 July 2013 diff hist +273 Visual circuit tutorial Add temporary link to hopefully un-confusing thread
19 July 2013
- 19:4719:47, 19 July 2013 diff hist +121 PPU rendering Specify where the flag and X position loading happens during sprite loading (derived from Visual 2C02)
17 July 2013
- 20:3920:39, 17 July 2013 diff hist +90 PPU registers Probably best to just ignore writes to $2004 during rendering for emulation
- 20:3620:36, 17 July 2013 diff hist +1 m PPU registers No edit summary
- 20:3520:35, 17 July 2013 diff hist +109 PPU registers Sprite evaluation status might affect the glitchy OAMADDR increment when accessing OAMDATA during rendering
- 20:3120:31, 17 July 2013 diff hist +392 PPU registers Writes to OAMDATA during rendering do not modify memory but do bump OAMADDR in a glitchy way
- 17:4017:40, 17 July 2013 diff hist +180 PPU sprite evaluation Add internal details on the secondary OAM clear
- 16:1916:19, 17 July 2013 diff hist +8 m PPU sprite evaluation No edit summary
- 16:1716:17, 17 July 2013 diff hist +1,161 PPU sprite evaluation Add likely explanation for the sprite overflow bug, derived from Visual 2C02
16 July 2013
- 08:3808:38, 16 July 2013 diff hist +5,145 User:Ulfalizer Add signal trace for possible sprite overflow bug explanation
15 July 2013
- 17:4417:44, 15 July 2013 diff hist +232 Visual circuit tutorial The DRAM rows become consecutive if we reverse the row selection bits
14 July 2013
- 15:0615:06, 14 July 2013 diff hist +147 Talk:INES Last 4
- 09:4509:45, 14 July 2013 diff hist +368 Talk:INES Dirty ROM detection
12 July 2013
- 13:0413:04, 12 July 2013 diff hist +125 Visual circuit tutorial Add link to transistor video on YouTube
5 July 2013
- 23:3723:37, 5 July 2013 diff hist 0 User:Ulfalizer Mystery tick for sprite zero should read as 1 if ignoring propagation delays
- 23:0123:01, 5 July 2013 diff hist 0 m User:Ulfalizer No edit summary
- 23:0023:00, 5 July 2013 diff hist +1,228 User:Ulfalizer Add timing for sprite zero/overflow flag clearing
- 00:5500:55, 5 July 2013 diff hist +270 User:Ulfalizer Add Visual 6502 IRQ link for reset
- 00:0400:04, 5 July 2013 diff hist +396 User:Ulfalizer Add Visual 6502 IRQ links for interrupt hijacking
4 July 2013
- 22:1222:12, 4 July 2013 diff hist +3 m User:Ulfalizer No edit summary
- 22:1222:12, 4 July 2013 diff hist +519 User:Ulfalizer Add Visual 6502 IRQ links for RTI/CLI/SEI/PLP
- 21:0821:08, 4 July 2013 diff hist +401 User:Ulfalizer Add Visual 6502 IRQ links for JMP Absolute/Indirect
- 20:2620:26, 4 July 2013 diff hist +723 User:Ulfalizer Add Visual 6502 IRQ links for branches
- 19:0019:00, 4 July 2013 diff hist +6 User:Ulfalizer Add ~NMIG signal to trace for NMI link
3 July 2013
- 17:2817:28, 3 July 2013 diff hist +6 User:Ulfalizer Add State to NMI link
- 16:1616:16, 3 July 2013 diff hist +25 User:Ulfalizer Add nnT2BR and 646 (some kind of "sampling points for IRQ" signal) to the interrupt links
- 16:0016:00, 3 July 2013 diff hist −88 User:Ulfalizer Correct IRQ sampling location and add conditions
- 15:5115:51, 3 July 2013 diff hist +22 User:Ulfalizer Add IRQP and State to Visual 6502 interrupt links
- 09:2209:22, 3 July 2013 diff hist +66 The skinny on NES scrolling Status of increment bit does not influence what happens for $2007 access during rendering
2 July 2013
- 20:0320:03, 2 July 2013 diff hist −4 m Tricky-to-emulate games No edit summary
- 20:0220:02, 2 July 2013 diff hist +9 m Tricky-to-emulate games No edit summary
- 12:0212:02, 2 July 2013 diff hist +79 Tricky-to-emulate games Add PPU palettes link for Micro Machines
- 11:5311:53, 2 July 2013 diff hist +14 Tricky-to-emulate games It's cannon balls, not bombs
- 11:5211:52, 2 July 2013 diff hist +298 Tricky-to-emulate games The Young Indiana Jones Chronicles accesses $2007 during rendering
- 11:2211:22, 2 July 2013 diff hist +399 PPU registers Flesh out master/slave mode description
- 10:1510:15, 2 July 2013 diff hist +397 Talk:PPU palettes Background palette hack and output to EXT pins
- 09:5809:58, 2 July 2013 diff hist +227 Talk:PPU palettes Unused palette data and EXT pins
- 08:5108:51, 2 July 2013 diff hist +89 Visual circuit tutorial Link org's PPU analysis too
1 July 2013
- 19:0819:08, 1 July 2013 diff hist +54 PPU palettes Mention chroma and luma
- 14:4514:45, 1 July 2013 diff hist +150 PPU palettes The background palette "hack" is an intentional feature of the PPU
30 June 2013
- 09:2809:28, 30 June 2013 diff hist +8 Visual circuit tutorial Has contributions from more people now, so don't imply I wrote everything
29 June 2013
- 03:4303:43, 29 June 2013 diff hist −5 Visual circuit tutorial Use "zeroth" instead of "bottom-most" since it gets a bit confusing with the bit being at the top of the adder
- 03:3103:31, 29 June 2013 diff hist +18 m Visual circuit tutorial Style tweaks
28 June 2013
- 15:0815:08, 28 June 2013 diff hist +124 Visual circuit tutorial Add link to PPU overview image.
- 15:0315:03, 28 June 2013 diff hist +251 Visual circuit tutorial Add link for extra node names repo.
- 14:4814:48, 28 June 2013 diff hist +41 N File:Ppuareas.png Overview of how the NTSC PPU is laid out. current
- 05:1605:16, 28 June 2013 diff hist +529 The skinny on NES scrolling The story with $2007 access during rendering is more complicated (but also pretty straightforward)
- 02:5202:52, 28 June 2013 diff hist +44 PPU power up state Reset signal only clears loopy's t, not v
27 June 2013
- 18:4918:49, 27 June 2013 diff hist +2 PPU power up state Reset signals sets up an even frame
- 18:3018:30, 27 June 2013 diff hist +33 PPU power up state Internal reset signal also clears the $2007 read buffer
- 18:2318:23, 27 June 2013 diff hist +17 PPU power up state Clarify that dot 1 is the second dot
- 18:1918:19, 27 June 2013 diff hist +22 PPU power up state Fine x scroll is also cleared by the internal reset signal
- 18:1518:15, 27 June 2013 diff hist +396 PPU power up state Fill in details derived from Visual 2C02 for what happens on reset
18 June 2013
- 21:3721:37, 18 June 2013 diff hist +9 m Talk:PPU rendering Wups... wasn't logged in
17 June 2013
- 08:4008:40, 17 June 2013 diff hist +5,034 User:Ulfalizer Add some timing charts so I don't lose them
16 June 2013
- 13:1013:10, 16 June 2013 diff hist +6 m Visual circuit tutorial No edit summary
14 June 2013
- 16:3916:39, 14 June 2013 diff hist +6 m Visual circuit tutorial No edit summary
- 16:3716:37, 14 June 2013 diff hist +193 Visual circuit tutorial Add info on apu_clk2x signals
- 16:1316:13, 14 June 2013 diff hist +237 Visual circuit tutorial Superbuffers often appear on circuits with a large fan-out
13 June 2013
- 15:5615:56, 13 June 2013 diff hist +9 APU Frame Counter Also specify reg
- 15:5515:55, 13 June 2013 diff hist +234 APU Frame Counter Add overview for the frame interrupt flag
- 05:5405:54, 13 June 2013 diff hist −2 m Visual circuit tutorial Use "similar" instead of "identical". You don't get lines and their inverses running in the mask ROM for example.
- 04:3304:33, 13 June 2013 diff hist +309 Game bugs Junk tiles in the overscan
12 June 2013
- 00:3500:35, 12 June 2013 diff hist +1 m APU Length Counter No edit summary current
- 00:3400:34, 12 June 2013 diff hist +145 APU Length Counter Might as well fill in the interpretation for base length 10 too
- 00:1100:11, 12 June 2013 diff hist 0 m Visual circuit tutorial No edit summary
11 June 2013
- 05:4305:43, 11 June 2013 diff hist −28 Visual circuit tutorial CPU pinout page doesn't mention RDY, so don't link it
- 05:1105:11, 11 June 2013 diff hist +1,282 Visual circuit tutorial Add section on 6502 cycle and phase timing
- 04:2204:22, 11 June 2013 diff hist +72 Visual circuit tutorial Precharge logic is now active in Visual 2C02
- 02:1902:19, 11 June 2013 diff hist +35 Visual circuit tutorial Be more specific than "left" and "right" now that there are three images for the cross-coupled inverter
- 02:0102:01, 11 June 2013 diff hist +99 Visual circuit tutorial Output drivers neither source nor sink for reads too
- 01:5501:55, 11 June 2013 diff hist −4 Visual circuit tutorial s/generates/sinks/ ("source" and "generate" are synonyms :P)
- 01:5301:53, 11 June 2013 diff hist +181 Visual circuit tutorial Output drivers can be tri-stated by activating neither the pull-up nor the pull-down transistors
- 00:5100:51, 11 June 2013 diff hist −11 CPU interrupts Interrupt polling actually happens on the falling edge of φ2
9 June 2013
- 23:1723:17, 9 June 2013 diff hist +524 Visual circuit tutorial Add note on master clock and CPU/PPU clock alignment
6 June 2013
- 22:2322:23, 6 June 2013 diff hist +67 User:Ulfalizer loopy_v writes use the same timing too
- 22:0922:09, 6 June 2013 diff hist +22 User:Ulfalizer Need to figure out setting timing for spr_overflow
- 22:0922:09, 6 June 2013 diff hist +64 User:Ulfalizer spr_overflow is read the same too
- 21:5621:56, 6 June 2013 diff hist +59 User:Ulfalizer spr0_hit is read like vbl_flag
- 21:4721:47, 6 June 2013 diff hist +60 User:Ulfalizer Add spr0_hit timing
- 21:2721:27, 6 June 2013 diff hist +1,062 Talk:Visual circuit tutorial Sizing current
- 16:3516:35, 6 June 2013 diff hist 0 User:Ulfalizer s/db/ab/
- 14:0414:04, 6 June 2013 diff hist −1 m Visual circuit tutorial No edit summary
- 11:4211:42, 6 June 2013 diff hist +293 Visual circuit tutorial Add note on hashes and tildes on Visual 6502 node names (
- 01:4301:43, 6 June 2013 diff hist +1 m User:Ulfalizer No edit summary
5 June 2013
- 22:2322:23, 5 June 2013 diff hist +13 User:Ulfalizer _io_ce actually follows inverted M2
- 21:3921:39, 5 June 2013 diff hist +91 User:Ulfalizer More vbl_flag details
- 21:2721:27, 5 June 2013 diff hist +118 User:Ulfalizer vbl_flag timing
- 20:5720:57, 5 June 2013 diff hist +33 User:Ulfalizer _io_ce follows M2
- 20:5420:54, 5 June 2013 diff hist +87 User:Ulfalizer No built-in delay for '''rw''' in PPU
- 20:4920:49, 5 June 2013 diff hist +1,229 User:Ulfalizer Add signal timing from address decoder
- 20:2220:22, 5 June 2013 diff hist −35 m User:Ulfalizer No edit summary
- 19:5419:54, 5 June 2013 diff hist +103 User:Ulfalizer Add link to IRQ pin
- 19:5219:52, 5 June 2013 diff hist +50 User:Ulfalizer rw changes during φ1
- 19:5019:50, 5 June 2013 diff hist +35 User:Ulfalizer Add ns timing for M2 duty cycle
- 19:4319:43, 5 June 2013 diff hist +53 User:Ulfalizer Address set during φ1
- 19:4119:41, 5 June 2013 diff hist +671 User:Ulfalizer Add interrupt timing info
- 19:2519:25, 5 June 2013 diff hist +65 User:Ulfalizer Add quick link to clocks section of tutorial
- 19:2419:24, 5 June 2013 diff hist +173 User:Ulfalizer Read/writes seem to happen during φ2
- 19:1519:15, 5 June 2013 diff hist +2,090 N User:Ulfalizer Bring together various timing stuff in one place
- 10:5210:52, 5 June 2013 diff hist 0 m Talk:Visual circuit tutorial No edit summary
- 10:5110:51, 5 June 2013 diff hist +534 Talk:Visual circuit tutorial Component sizing
4 June 2013
- 11:1711:17, 4 June 2013 diff hist −5 m Talk:Visual circuit tutorial No edit summary
- 10:5910:59, 4 June 2013 diff hist +380 Talk:Visual circuit tutorial Circuit notation
- 10:5510:55, 4 June 2013 diff hist +285 Visual circuit tutorial Explain multiplexer
- 10:4310:43, 4 June 2013 diff hist +12 Visual circuit tutorial Boldface "VBlank"
- 10:4210:42, 4 June 2013 diff hist +4 Visual circuit tutorial Rephrase wire capacitance description a bit
- 10:3710:37, 4 June 2013 diff hist +490 Visual circuit tutorial Explain "floating" terminology and move wire capacitance section first to eliminate some backreferences
3 June 2013
- 14:2214:22, 3 June 2013 diff hist −14 APU Length Counter Fix link to internal table
- 11:2011:20, 3 June 2013 diff hist +240 Visual circuit tutorial Link to image of similar circuit for clocked latch
- 11:1311:13, 3 June 2013 diff hist 0 Visual circuit tutorial PLA wikipedia link was broken
- 10:5810:58, 3 June 2013 diff hist +10 Visual circuit tutorial Be a bit clearer about m-to-n for decoders
- 10:5410:54, 3 June 2013 diff hist −5 m Visual circuit tutorial No edit summary
- 10:5310:53, 3 June 2013 diff hist +378 Visual circuit tutorial Mention PLAs in conjunction with decoders and mask ROMs
- 10:4610:46, 3 June 2013 diff hist 0 Visual circuit tutorial Forgot to change the PLA picture
- 10:4610:46, 3 June 2013 diff hist +343 Visual circuit tutorial Rephrase PLA section in terms of decoder and mask ROMs
- 09:3809:38, 3 June 2013 diff hist +43 Visual circuit tutorial Add link to skinny for fine_x
- 09:3509:35, 3 June 2013 diff hist +3,171 Visual circuit tutorial Add section on shift registers
- 09:1109:11, 3 June 2013 diff hist +60 N File:Vis shift reg zoom.png Zoomed-in shift register for Visual 6502/2C02/2A03 tutorial.
- 09:1009:10, 3 June 2013 diff hist +50 N File:Vis shift reg.png Shift register for Visual 6502/2C02/2A03 tutorial.
2 June 2013
- 20:2420:24, 2 June 2013 diff hist +36 NES reference guide Diagram is still useful for NES
- 20:0120:01, 2 June 2013 diff hist +224 Talk:Visual circuit tutorial PLA
- 19:4219:42, 2 June 2013 diff hist +2 m Talk:Visual circuit tutorial No edit summary
- 19:4019:40, 2 June 2013 diff hist +452 Talk:Visual circuit tutorial PLA
- 19:2319:23, 2 June 2013 diff hist 0 m Talk:Visual circuit tutorial No edit summary
- 19:2219:22, 2 June 2013 diff hist +272 Talk:Visual circuit tutorial PLA
- 18:5718:57, 2 June 2013 diff hist +285 Talk:Visual circuit tutorial PLA
- 16:0316:03, 2 June 2013 diff hist −312 Visual circuit tutorial Avoid the door analogy for gates (see http://forum.6502.org/viewtopic.php?f=1&t=2522&sid=9a19537b5579d427d670c45357dcbf07&start=15)
- 13:2113:21, 2 June 2013 diff hist +162 Visual circuit tutorial Mention "don't care" conditions for PLAs
- 10:0410:04, 2 June 2013 diff hist +53 Visual circuit tutorial Mention pull-up resistors in 'power sources' section
- 09:5209:52, 2 June 2013 diff hist +65 APU Length Counter Add link to visual circuit tutorial for the internal table
- 07:3907:39, 2 June 2013 diff hist +148 Visual circuit tutorial Add interpretation for one of the adder columns
- 07:0907:09, 2 June 2013 diff hist +224 Talk:Visual circuit tutorial Combined DRAM picture
- 07:0507:05, 2 June 2013 diff hist +55 Visual circuit tutorial Might be missed the first time, so add terms link for "via" in DRAM section too (probably overkill after that though)
1 June 2013
- 20:4920:49, 1 June 2013 diff hist +157 Talk:Visual circuit tutorial Redraws
- 20:1420:14, 1 June 2013 diff hist +4 Visual circuit tutorial The values on the gates and not the gates themselves are the inputs to the NORs (while I'm nitpicking myself :P)
- 20:0520:05, 1 June 2013 diff hist +9 m Visual circuit tutorial No edit summary
- 19:5919:59, 1 June 2013 diff hist +278 Talk:Visual circuit tutorial No edit summary
- 19:5419:54, 1 June 2013 diff hist −4 Visual circuit tutorial You don't really get a current (except initially) in the steady state unless it goes to ground, so use "current" instead of "the current"
- 19:4919:49, 1 June 2013 diff hist +311 Talk:Visual circuit tutorial No edit summary
- 19:3919:39, 1 June 2013 diff hist −2 m Visual circuit tutorial No edit summary
- 19:3819:38, 1 June 2013 diff hist −2 Visual circuit tutorial Polish NOR description a bit
- 19:2319:23, 1 June 2013 diff hist −1 Visual circuit tutorial De-parenthesize
- 19:1419:14, 1 June 2013 diff hist 0 Visual circuit tutorial Settle on American spelling of "gray" (wasn't sure which one it was :P)
- 19:0219:02, 1 June 2013 diff hist +6 Visual circuit tutorial I still think a "hence" sounds better here
- 19:0019:00, 1 June 2013 diff hist +4 Visual circuit tutorial Be more specific about which open gates
- 18:5518:55, 1 June 2013 diff hist +3 m Visual circuit tutorial No edit summary
- 18:5518:55, 1 June 2013 diff hist +78 Visual circuit tutorial Add current formulation for NOR gates section
- 18:5018:50, 1 June 2013 diff hist −1 Visual circuit tutorial s/white/grey/
- 18:4818:48, 1 June 2013 diff hist +19 Visual circuit tutorial Be more specific about the NOR
- 18:4718:47, 1 June 2013 diff hist −101 Visual circuit tutorial The highlight colors are no longer different in the picture
- 18:4618:46, 1 June 2013 diff hist +71 Visual circuit tutorial The picture for the cross-coupled inverter no longer matched the text
- 18:3418:34, 1 June 2013 diff hist +326 Talk:Visual circuit tutorial Steady state
- 18:1018:10, 1 June 2013 diff hist +162 m Talk:Visual circuit tutorial No edit summary
- 17:5417:54, 1 June 2013 diff hist +842 Talk:Visual circuit tutorial Steady state, currents, and voltages
