Standard controller: Difference between revisions

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== Hardware ==
== Hardware ==


The 4021 (or [http://www.datasheetcatalog.org/datasheet/philips/74HC_HCT165_CNV_2.pdf 74LS165]) IC is an 8-bit parallel-to-serial shift
The [https://www.ti.com/lit/ds/symlink/cd4021b-q1.pdf 4021] (or [http://www.datasheetcatalog.org/datasheet/philips/74HC_HCT165_CNV_2.pdf 74LS165]) IC is an 8-bit parallel-to-serial shift
register. It has a pin "serial input", ordinarily used to chain the output of one shift register into the next one as seen in the Four Score or the Super NES controller. The serial input on the tail end of such a chain (or the only one in the case of an NES) can be tied to ground or Vcc, which determines the state of the output after all bits have been shifted out. If this is grounded, the shift register produces a 0 after all bits have been shifted out; if it's tied to Vcc, it produces a 1.
register. It has a pin "serial input", ordinarily used to chain the output of one shift register into the next one as seen in the Four Score or the Super NES controller. The serial input on the tail end of such a chain (or the only one in the case of an NES) can be tied to ground or Vcc, which determines the state of the output after all bits have been shifted out. If this is grounded, the shift register produces a 0 after all bits have been shifted out; if it's tied to Vcc, it produces a 1.



Revision as of 07:56, 28 January 2023

All NES units come with at least one standard controller - without it, you wouldn't be able to play any games!

Standard controllers can be used in both controller ports, or in a Four score accessory.

For code examples, see: Controller reading code

Report

The standard NES controller will report 8 bits on its data line:

0 - A
1 - B
2 - Select
3 - Start
4 - Up
5 - Down
6 - Left
7 - Right

After 8 bits are read, all subsequent bits will report 1 on a standard NES controller, but third party and other controllers may report other values here.

If using DPCM audio samples, read conflicts must be corrected with a software technique. The most common symptom of this is spurious Right presses as the DPCM conflict deletes one bit of the report, and an extra 1 bit appears in the Right press position. See: Controller reading: DPCM conflict.

Input ($4016 write)

7  bit  0
---- ----
xxxx xxxS
        |
        +- Controller shift register strobe

While S (strobe) is high, the shift registers in the controllers are continuously reloaded from the button states, and reading $4016/$4017 will keep returning the current state of the first button (A). Once S goes low, this reloading will stop. Hence a 1/0 write sequence is required to get the button states, after which the buttons can be read back one at a time.

(Note that bits 2-0 of $4016/write are stored in internal latches in the 2A03/07.)

Output ($4016/$4017 read)

7  bit  0
---- ----
xxxx xMES
      |||
      ||+- Primary controller status bit
      |+-- Expansion controller status bit (Famicom)
      +--- Microphone status bit (Famicom, $4016 only)

Though both are polled from a write to $4016, controller 1 is read through $4016, and controller 2 is separately read through $4017.

Each read reports one bit at a time through D0. The first 8 reads will indicate which buttons or directions are pressed (1 if pressed, 0 if not pressed). All subsequent reads will return 1 on official Nintendo brand controllers but may return 0 on third party controllers such as the U-Force.

Status for each controller is returned as an 8-bit report in the following order: A, B, Select, Start, Up, Down, Left, Right.

In the NES and Famicom, the top three (or five) bits are not driven, and so retain the bits of the previous byte on the bus. Usually this is the most significant byte of the address of the controller port—0x40. Certain games (such as Paperboy) rely on this behavior and require that reads from the controller ports return exactly $40 or $41 as appropriate. See: Controller reading: unconnected data lines.

When no controller is connected, the corresponding status bit will report 0. This is due to the presence of internal pull-up resistors, and the internal inverter. (See: Controller reading)

Famicom

The original Famicom's hard-wired second controller (II) is missing the Select and Start buttons. Its corresponding bits will read as 0, so Famicom games do not rely on the second player being able to push Start or Select.

This hard-wired second controller also contains a microphone, which gives an immediate 1-bit report at $4016 D2 whenever it is read.

The later AV Famicom used detachable controllers, with connectors identical to the NES. Its second controller was the same as the first, with Select and Start present, and no microphone.

The expansion port of the Famicom could be used to connect external controllers. These gave the same standard 8-bit report, but through D1 instead of D0. It was common for Famicom games to combine D1 and D0 (logical OR) when reading to permit players to use expansion controllers instead, though several games do not support this[1]. Alternatively, these could be used as extra controllers for 4-player games.

Hardware

The 4021 (or 74LS165) IC is an 8-bit parallel-to-serial shift register. It has a pin "serial input", ordinarily used to chain the output of one shift register into the next one as seen in the Four Score or the Super NES controller. The serial input on the tail end of such a chain (or the only one in the case of an NES) can be tied to ground or Vcc, which determines the state of the output after all bits have been shifted out. If this is grounded, the shift register produces a 0 after all bits have been shifted out; if it's tied to Vcc, it produces a 1.

The 4021 has a parallel/serial control pin connected to OUT0 ($4016 bit 0). When this goes high (parallel mode), the current controller state is directly captured by the 8 bits of its shift register. When it returns to low (serial mode) the bits in the register will be shifted once for every rising edge of CLK. CLK is normally high, but goes low before the read from $4016 or $4017, then returns high after the read, creating the rising edge that will shift the next bit into place.

In the NES controller, this input is grounded. But because the signals from the controllers pass through an inverter before reaching the CPU, the register produces a 1 for all reads after the first eight.

If using DPCM audio samples, read conflicts may occur requiring a software technique to correct for them. See: Controller reading: DPCM conflict.

PAL

Some PAL region consoles have internal diodes on their controller port. (See: Controller port pinout: PAL)

These diodes prevent the Clock and Latch signals from functioning unless they are pulled high. PAL controllers for these regions (NES-004) each contain a 3.6KΩ resistor between these two inputs and 5V.[2]

On these systems, only PAL controllers with the pull-ups can be read. NTSC systems can read controllers of either type. Modifying the internal controller port to bypass these diodes will make the PAL system compatible with both. Conversely, modifying a controller to add the pull-up resistors makes it compatible with both types of systems.

Turbo

A turbo controller such as the NES Max or NES Advantage is read just like a standard controller, but the user can switch some of its buttons to be toggled by an oscillator. Such an oscillator turns the button on and off at 15 to 30 Hz, producing rapid fire in games.

A controller should not toggle the button states on each strobe pulse. Doing so will cause problems for games that poll the controller in a loop until they get two identical consecutive reads (see DMC conflict above). The game may halt while the turbo button is held, or crash, or cause other unknown behaviour.

See also

References

  1. Famicom World forum post: Famicom games that do not work with pads connected through the expansion port.
  2. Forum post: explaining PAL controller diodes and their function.
  • Forum post: Famicom controller PCB and exterior photographs