Standard controller: Difference between revisions

From NESdev Wiki
Jump to navigationJump to search
(Adds NES and Famicom player 2 controller images.)
 
(19 intermediate revisions by 3 users not shown)
Line 1: Line 1:
[[File:NES-Controller-Flat.jpg|400px|thumb|right|Standard NES controller]]
All NES units come with at least one standard controller - without it, you wouldn't be able to play any games!
All NES units come with at least one standard controller - without it, you wouldn't be able to play any games!


Standard controllers can be used in both controller ports, or in a [[Four score]] accessory.
Standard controllers can be used in both controller ports, or in a [[Four score]] accessory.


:''For code examples, see: [[Controller Reading]]''
:''For code examples, see: [[Controller reading code]]''


=== Input ($4016 write) ===
== Report ==
The standard NES controller will report 8 bits on its data line:
 
0 - A
1 - B
2 - Select
3 - Start
4 - Up
5 - Down
6 - Left
7 - Right
 
After 8 bits are read, all subsequent bits will report 1 on a standard NES controller, but third party and other controllers may report other values here.
 
If using DPCM audio samples, read conflicts must be corrected with a software technique. The most common symptom of this is spurious Right presses as the DPCM
conflict deletes one bit of the report, and an extra 1 bit appears in the Right press position. See: [[Controller reading#DPCM conflict|Controller reading: DPCM conflict]].
 
== Input ($4016 write) ==


  7  bit  0
  7  bit  0
Line 17: Line 35:
(Note that bits 2-0 of $4016/write are stored in internal latches in the 2A03/07.)
(Note that bits 2-0 of $4016/write are stored in internal latches in the 2A03/07.)


=== Output ($4016/$4017 read) ===
== Output ($4016/$4017 read) ==
 
NES-001 (front-loading NES) $4016 and $4017, and NES-101 (top-loading NES) $4016 and $4017
7  bit  0
---- ----
oooX XZXD
|||| ||||
|||| |||+- Serial controller data
|||+-+-+-- Always 0
|||  +--- Open bus on NES-101 $4016; 0 otherwise
+++------- Open bus
 
Famicom $4016:
7  bit  0
---- ----
oooo oMFD
|||| ||||
|||| |||+- Player 1 serial controller data
|||| ||+-- If connected to expansion port (and available), player 3 serial controller data (0 otherwise)
|||| |+--- Microphone in controller 2 on traditional Famicom, 0 on AV Famicom
++++-+---- Open bus


Famicom $4017:
  7  bit  0
  7  bit  0
  ---- ----
  ---- ----
  oooX XXFD
  xxxx xMES
|||| ||||
      |||
|||| |||+- Player 2 serial controller data
      ||+- Primary controller status bit
|||| ||+-- If connected to expansion port, player 4 serial controller data (0 otherwise)
      |+-- Expansion controller status bit (Famicom)
|||+-+++-- Returns 0 unless something is plugged into the [[Famicom expansion port pinout|Famicom expansion port]]
      +--- Microphone status bit (Famicom, $4016 only)
+++------- Open bus
 
The first 8 reads will indicate which buttons are pressed (1 if pressed, 0 if not pressed).
All subsequent reads will return D=1 on a Nintendo brand controller but may return D=0 on third party controllers such as the [[U-Force]].
 
Button status for each controller is returned as an 8-bit report in the following order: A, B, Select, Start, Up, Down, Left, Right.
On plug-in controllers (the NES and AV Famicom) and the first controller of the original Famicom, all buttons are present.
However, on the original Famicom's second controller the Select and Start buttons are absent, and the encoder chip returns 0 instead: A, B, 0, 0, Up, Down, Left, Right.
Because these buttons do not exist, games for the Famicom should never require the second player to press Select or Start.


In the NES and Famicom, the top three (or five) bits are not driven, and so retain the bits of the previous byte on the bus. Usually this is the most significant byte of the address of the controller port—0x40. Certain games (such as Paperboy) rely on this behavior and require that reads from the controller ports return exactly $40 or $41 as appropriate.
Though both are polled from a write to $4016, controller 1 is read through $4016, and controller 2 is separately read through $4017.


Due to the presence of internal pull-up resistors, and the internal inverter, any pin without power connected will return zero, as shown above in the diagrams.
Each read reports one bit at a time through D0. The first 8 reads will indicate which buttons or directions are pressed (1 if pressed, 0 if not pressed).
All subsequent reads will return 1 on official Nintendo brand controllers but may return 0 on third party controllers such as the [[U-Force]].


Because the Famicom controllers are permanently attached, some games (such as Castlevania II - Simon's Quest) allow the use of the player 3 and 4 data for players 1 and 2.
Status for each controller is returned as an 8-bit report in the following order: A, B, Select, Start, Up, Down, Left, Right.


A [[SNES controller|Super NES controller]] can be wired to the NES controller port, and it returns a 16-bit report in a similar order: B, Y, Select, Start, Up, Down, Left, Right, then A, X, L, R, and four 0 bits.
In the NES and Famicom, the top three (or five) bits are not driven, and so retain the bits of the previous byte on the bus. Usually this is the most significant byte of the address of the controller port—0x40. Certain games (such as Paperboy) rely on this behavior and require that reads from the controller ports return exactly $40 or $41 as appropriate. ''See: [[Controller reading#Unconnected data lines and open bus|Controller reading: unconnected data lines]].''


=== Hardware ===
When no controller is connected, the corresponding status bit will report 0. This is due to the presence of internal pull-up resistors, and the internal inverter. (See: [[Controller reading]])


The 4021 (or [http://www.datasheetcatalog.org/datasheet/philips/74HC_HCT165_CNV_2.pdf 74LS165]) IC is an 8-bit parallel-to-serial shift
=== Famicom ===
register. It has a pin "serial input", ordinarily used to chain the output of one shift register into the next one as seen in the Four Score or the Super NES controller. The serial input on the tail end of such a chain (or the only one in the case of an NES) can be tied to ground or Vcc, which determines the state of the output after all bits have been shifted out. If this is grounded, the shift register produces a 0 after all bits have been shifted out; if it's tied to Vcc, it produces a 1.


In the NES controller, this input is grounded. But because the signals from the controllers pass through an inverter before reaching the CPU, the register produces a 1 for all reads after the first eight.
[[File:Nintendo-Famicom-Controller-II-FL.jpg|200px|thumb|right|Famicom second-player controller]]
The original Famicom's hard-wired second controller (II) is missing the Select and Start buttons. Its corresponding bits will read as 0, so Famicom games do not rely on the second player being able to push Start or Select.


<span id="Bit_deletion"></span><span id="Double clock"></span>
This hard-wired second controller also contains a microphone, which gives an immediate 1-bit report at $4016 D2 whenever it is read.


=== <span id="Evil_Details">APU DMC conflict glitch</span> ===
The later AV Famicom used detachable controllers, with connectors identical to the NES. Its second controller was the same as the first, with Select and Start present, and no microphone.


The CLK line for controller port is ''R/W nand (ADDRESS == $4016/$4017)'' (i.e., CLK is low only when reading $4016/$4017, since R/W high means read). When this transitions from high to low, the buffer inside the NES latches the output of the controller data lines, and when it transitions from low to high, the shift register in the controller shifts one bit.<ref>[http://forums.nesdev.org/viewtopic.php?t=4116 Forum post:] DPCM generates extra $4016 read pulse</ref>
The expansion port of the Famicom could be used to connect external controllers. These gave the same standard 8-bit report, but through D1 instead of D0. It was common for Famicom games to combine D1 and D0 (logical OR) when reading to permit players to use expansion controllers instead, though several games do not support this<ref>[https://www.famicomworld.com/forum/index.php?topic=6701.msg167005#msg167005 Famicom World forum post]: Famicom games that do not work with pads connected through the expansion port.</ref>. Alternatively, these could be used as extra controllers for [[Four Score|4-player]] games.
<div style="clear: both"></div>


This can cause glitches if the [[APU DMC|DMC]] DMA is running, and happens to start a read in the same cycle that the CPU is trying to read from $4016 or $4017. Since the address bus will change for one cycle, the shift register will see an extra rising clock edge (a "double clock"), and the shift register will drop a bit out.
== Hardware ==
The program will see this as a '''bit deletion''' from the serial data.
Not correcting for this results in spurious presses, especially of Right.


This glitch is fixed in the 2A07 CPU used in the PAL NES.
The [https://www.ti.com/lit/ds/symlink/cd4021b-q1.pdf 4021] (or [http://www.datasheetcatalog.org/datasheet/philips/74HC_HCT165_CNV_2.pdf 74LS165]) IC is an 8-bit parallel-to-serial shift
register. It has a pin "serial input", ordinarily used to chain the output of one shift register into the next one as seen in the Four Score or the Super NES controller. The serial input on the tail end of such a chain (or the only one in the case of an NES) can be tied to ground or Vcc, which determines the state of the output after all bits have been shifted out. If this is grounded, the shift register produces a 0 after all bits have been shifted out; if it's tied to Vcc, it produces a 1.


This detail is poorly represented in emulators. Because it is not normally a compatibility issue, many emulators do not simulate this glitch at all.
The 4021 has a parallel/serial control pin connected to ''[[Controller port pinout|OUT0]]'' ($4016 bit 0). When this goes high (parallel mode), the current controller state is directly captured by the 8 bits of its shift register. When it returns to low (serial mode) the bits in the register will be shifted once for every rising edge of ''CLK''. CLK is normally high, but goes low before the read from $4016 or $4017, then returns high after the read, creating the rising edge that will shift the next bit into place.


==== Multiple Read Solution ====
In the NES controller, this input is grounded. But because the signals from the controllers pass through an inverter before reaching the CPU, the register produces a 1 for all reads after the first eight.


The standard solution used in most games using DMC will read the controller multiple times and compare the results to avoid this problem.
If using DPCM audio samples, read conflicts may occur requiring a software technique to correct for them. See: [[Controller reading#DPCM conflict|Controller reading: DPCM conflict]].


See [[Controller Reading]] for examples.
=== PAL ===


==== Synchronized OAM Solution ====
Some PAL region consoles have internal diodes on their controller port. (See: [[Controller port pinout#PAL|Controller port pinout: PAL]])


Because OAM DMA synchronizes the CPU and APU such that reads on an "even" CPU cycle never overlap a glitch, a program on an NTSC NES can miss all the glitches by triggering an OAM DMA as the last thing in vblank just before reading the controller, so long as all the reads are spaced an even number of cycles apart.<ref>[http://forums.nesdev.org/viewtopic.php?p=171971 Forum post:] Rahsennor's OAM-synchronized controller read</ref>
These diodes prevent the Clock and Latch signals from functioning unless they are pulled high. PAL controllers for these regions (NES-004) each contain a 3.6KΩ resistor between these two inputs and 5V.<ref>[//forums.nesdev.org/viewtopic.php?p=238272#p238272 Forum post]: explaining PAL controller diodes and their function.</ref>


Because this is a relatively new discovery, many current emulated implementations of the DMC glitch may be inadequate for testing this technique<ref>[http://forums.nesdev.org/viewtopic.php?f=2&t=14319&start=15#p172194 Forum post:] as of May 2016, Nintendulator and Nestopia do not accurately emulate OAM-synchronized controller reading.</ref>. Hardware testing is recommended.
On these systems, only PAL controllers with the pull-ups can be read. NTSC systems can read controllers of either type. Modifying the internal controller port to bypass these diodes will make the PAL system compatible with both. Conversely, modifying a controller to add the pull-up resistors makes it compatible with both types of systems.


=== Turbo ===
== Turbo ==


A '''turbo controller''' such as the NES Max or NES Advantage is read just like a standard controller, but the user can switch some of its buttons to be toggled by an oscillator.
A '''turbo controller''' such as the NES Max or NES Advantage is read just like a standard controller, but the user can switch some of its buttons to be toggled by an oscillator.
Line 107: Line 96:


== See also ==
== See also ==
*[[Controller Reading]]
*[[Controller reading]]
*[[Controller detection]]
*[[Controller detection]]
*[[Controller port pinout]]
*[[Controller port pinout]]
*[[Four Score]] 4-player adapter
*[[SNES controller]] has backward compatible protocol with the NES


== References ==
== References ==

Latest revision as of 04:33, 18 January 2024

Standard NES controller

All NES units come with at least one standard controller - without it, you wouldn't be able to play any games!

Standard controllers can be used in both controller ports, or in a Four score accessory.

For code examples, see: Controller reading code

Report

The standard NES controller will report 8 bits on its data line:

0 - A
1 - B
2 - Select
3 - Start
4 - Up
5 - Down
6 - Left
7 - Right

After 8 bits are read, all subsequent bits will report 1 on a standard NES controller, but third party and other controllers may report other values here.

If using DPCM audio samples, read conflicts must be corrected with a software technique. The most common symptom of this is spurious Right presses as the DPCM conflict deletes one bit of the report, and an extra 1 bit appears in the Right press position. See: Controller reading: DPCM conflict.

Input ($4016 write)

7  bit  0
---- ----
xxxx xxxS
        |
        +- Controller shift register strobe

While S (strobe) is high, the shift registers in the controllers are continuously reloaded from the button states, and reading $4016/$4017 will keep returning the current state of the first button (A). Once S goes low, this reloading will stop. Hence a 1/0 write sequence is required to get the button states, after which the buttons can be read back one at a time.

(Note that bits 2-0 of $4016/write are stored in internal latches in the 2A03/07.)

Output ($4016/$4017 read)

7  bit  0
---- ----
xxxx xMES
      |||
      ||+- Primary controller status bit
      |+-- Expansion controller status bit (Famicom)
      +--- Microphone status bit (Famicom, $4016 only)

Though both are polled from a write to $4016, controller 1 is read through $4016, and controller 2 is separately read through $4017.

Each read reports one bit at a time through D0. The first 8 reads will indicate which buttons or directions are pressed (1 if pressed, 0 if not pressed). All subsequent reads will return 1 on official Nintendo brand controllers but may return 0 on third party controllers such as the U-Force.

Status for each controller is returned as an 8-bit report in the following order: A, B, Select, Start, Up, Down, Left, Right.

In the NES and Famicom, the top three (or five) bits are not driven, and so retain the bits of the previous byte on the bus. Usually this is the most significant byte of the address of the controller port—0x40. Certain games (such as Paperboy) rely on this behavior and require that reads from the controller ports return exactly $40 or $41 as appropriate. See: Controller reading: unconnected data lines.

When no controller is connected, the corresponding status bit will report 0. This is due to the presence of internal pull-up resistors, and the internal inverter. (See: Controller reading)

Famicom

Famicom second-player controller

The original Famicom's hard-wired second controller (II) is missing the Select and Start buttons. Its corresponding bits will read as 0, so Famicom games do not rely on the second player being able to push Start or Select.

This hard-wired second controller also contains a microphone, which gives an immediate 1-bit report at $4016 D2 whenever it is read.

The later AV Famicom used detachable controllers, with connectors identical to the NES. Its second controller was the same as the first, with Select and Start present, and no microphone.

The expansion port of the Famicom could be used to connect external controllers. These gave the same standard 8-bit report, but through D1 instead of D0. It was common for Famicom games to combine D1 and D0 (logical OR) when reading to permit players to use expansion controllers instead, though several games do not support this[1]. Alternatively, these could be used as extra controllers for 4-player games.

Hardware

The 4021 (or 74LS165) IC is an 8-bit parallel-to-serial shift register. It has a pin "serial input", ordinarily used to chain the output of one shift register into the next one as seen in the Four Score or the Super NES controller. The serial input on the tail end of such a chain (or the only one in the case of an NES) can be tied to ground or Vcc, which determines the state of the output after all bits have been shifted out. If this is grounded, the shift register produces a 0 after all bits have been shifted out; if it's tied to Vcc, it produces a 1.

The 4021 has a parallel/serial control pin connected to OUT0 ($4016 bit 0). When this goes high (parallel mode), the current controller state is directly captured by the 8 bits of its shift register. When it returns to low (serial mode) the bits in the register will be shifted once for every rising edge of CLK. CLK is normally high, but goes low before the read from $4016 or $4017, then returns high after the read, creating the rising edge that will shift the next bit into place.

In the NES controller, this input is grounded. But because the signals from the controllers pass through an inverter before reaching the CPU, the register produces a 1 for all reads after the first eight.

If using DPCM audio samples, read conflicts may occur requiring a software technique to correct for them. See: Controller reading: DPCM conflict.

PAL

Some PAL region consoles have internal diodes on their controller port. (See: Controller port pinout: PAL)

These diodes prevent the Clock and Latch signals from functioning unless they are pulled high. PAL controllers for these regions (NES-004) each contain a 3.6KΩ resistor between these two inputs and 5V.[2]

On these systems, only PAL controllers with the pull-ups can be read. NTSC systems can read controllers of either type. Modifying the internal controller port to bypass these diodes will make the PAL system compatible with both. Conversely, modifying a controller to add the pull-up resistors makes it compatible with both types of systems.

Turbo

A turbo controller such as the NES Max or NES Advantage is read just like a standard controller, but the user can switch some of its buttons to be toggled by an oscillator. Such an oscillator turns the button on and off at 15 to 30 Hz, producing rapid fire in games.

A controller should not toggle the button states on each strobe pulse. Doing so will cause problems for games that poll the controller in a loop until they get two identical consecutive reads (see DMC conflict above). The game may halt while the turbo button is held, or crash, or cause other unknown behaviour.

See also

References

  1. Famicom World forum post: Famicom games that do not work with pads connected through the expansion port.
  2. Forum post: explaining PAL controller diodes and their function.
  • Forum post: Famicom controller PCB and exterior photographs