Sunsoft 2 pinout: Difference between revisions

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m (oops, it does have bus conflicts)
m (switch to using CPU/PRG and PPU/CHR for extra clarity, also added links back to ines mappers.)
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                 .---\/---.       
                 .---\/---.       
  (r) PRG A15 <- |01    24| -- +5V
  (r) PRG A15 <- |01    24| -- +5V
  (r) PRG A14 <- |02    23| <- PRG A14 (n)
  (r) PRG A14 <- |02    23| <- PPU A14 (n)
  (r) PRG A16 <- |03    22| -> CHR nCS (r) *1
  (r) PRG A16 <- |03    22| -> CHR nCS (r) *1
   (s) PRG D7 -> |04    21| -> CHR A16 (r)
   (s) CPU D7 -> |04    21| -> CHR A16 (r)
   (s) PRG D6 -> |05    20| <- CHR nRD (s/n)
   (s) CPU D6 -> |05    20| <- PPU nRD (s/n)
   (s) PRG D5 -> |06    19| -> CHR A13 (r) *2
   (s) CPU D5 -> |06    19| -> CHR A13 (r) *2
   (s) PRG D4 -> |07    18| -> CHR A14 (r)
   (s) CPU D4 -> |07    18| -> CHR A14 (r)
   (s) PRG D3 -> |08    17| -> CHR A15 (r)
   (s) CPU D3 -> |08    17| -> CHR A15 (r)
   (s) PRG D2 -> |09    16| <- PRG nCE (s)
   (s) CPU D2 -> |09    16| <- /ROMSEL (s)
   (s) PRG D1 -> |10    15| <- PRG RnW (n)
   (s) CPU D1 -> |10    15| <- CPU RnW (n)
   (s) PRG D0 -> |11    14| <- CHR A13 (n)
   (s) CPU D0 -> |11    14| <- PPU A13 (n)
         GND -- |12    13| -> CIRAM A10 (n)
         GND -- |12    13| -> CIRAM A10 (n)
                 `--------'
                 `--------'
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  *2 CHR A13 is connected to CHR RAM's positive chip enable, so games that used CHR RAM must write 1 to it
  *2 CHR A13 is connected to CHR RAM's positive chip enable, so games that used CHR RAM must write 1 to it


The Sunsoft-2 mapper was found on the Sunsoft-3 and Sunsoft-3R boards,
The Sunsoft-2 mapper was found on the [[iNES Mapper 089|Sunsoft-3]] and [[iNES Mapper 093|Sunsoft-3R]] boards,
which are identical besides the default setting for the 9 configuration jumpers.
which are identical besides the default setting for the 9 configuration jumpers.


Line 25: Line 25:
Sunsoft-3 board for 128kB of CHR ROM.
Sunsoft-3 board for 128kB of CHR ROM.


* J1, J2  -  CHR's nWR/A14 input: J1=nWR, J2=A14
* J1, J2  -  CHR's nWR/A14 input: J1=PPU nWR, J2=SS2 A14
* J3, J4  -  mapper's CHR nRD input: J3=connected, J4= tied to ground
* J3, J4  -  SS2's PPU nRD input: J3=connected to PPU's nRD, J4= tied to ground
* J5, J6  -  CHR's nOE/A16 input: J5=A16, J6=nRD
* J5, J6  -  CHR's nOE/A16 input: J5=SS2 A16, J6=PPU nRD
* J7, J8, J9  -  mirroring: J7=horizontal, J8=vertical, J9=mapper-controlled one-screen
* J7, J8, J9  -  mirroring: J7=horizontal, J8=vertical, J9=mapper-controlled one-screen

Revision as of 23:58, 23 July 2012

Sunsoft-2: 24 pin shrink PDIP

               .---\/---.       
(r) PRG A15 <- |01    24| -- +5V
(r) PRG A14 <- |02    23| <- PPU A14 (n)
(r) PRG A16 <- |03    22| -> CHR nCS (r) *1
 (s) CPU D7 -> |04    21| -> CHR A16 (r)
 (s) CPU D6 -> |05    20| <- PPU nRD (s/n)
 (s) CPU D5 -> |06    19| -> CHR A13 (r) *2
 (s) CPU D4 -> |07    18| -> CHR A14 (r)
 (s) CPU D3 -> |08    17| -> CHR A15 (r)
 (s) CPU D2 -> |09    16| <- /ROMSEL (s)
 (s) CPU D1 -> |10    15| <- CPU RnW (n)
 (s) CPU D0 -> |11    14| <- PPU A13 (n)
        GND -- |12    13| -> CIRAM A10 (n)
               `--------'

*1 CHR nCS is the logical OR of CHR nRD and CHR A13, allowing them to use a 28-pin 128kB ROM
*2 CHR A13 is connected to CHR RAM's positive chip enable, so games that used CHR RAM must write 1 to it

The Sunsoft-2 mapper was found on the Sunsoft-3 and Sunsoft-3R boards, which are identical besides the default setting for the 9 configuration jumpers.

The Sunsoft-3R board was by default jumpered for 8kB of CHR RAM; the Sunsoft-3 board for 128kB of CHR ROM.

  • J1, J2 - CHR's nWR/A14 input: J1=PPU nWR, J2=SS2 A14
  • J3, J4 - SS2's PPU nRD input: J3=connected to PPU's nRD, J4= tied to ground
  • J5, J6 - CHR's nOE/A16 input: J5=SS2 A16, J6=PPU nRD
  • J7, J8, J9 - mirroring: J7=horizontal, J8=vertical, J9=mapper-controlled one-screen