TXC 05-00002-010 pinout: Difference between revisions
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(Figured out the 'carry' pin. appears to be complete.) |
(mention how mapper 173 both supports 64 KiB CHR but never actually had any) |
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| Line 39: | Line 39: | ||
Write $8000: [.... ....] - R[3,2,1,0] -> Q[3,2,1,0]. R4 XOR V -> Q4. | Write $8000: [.... ....] - R[3,2,1,0] -> Q[3,2,1,0]. R4 XOR V -> Q4. | ||
On mapper 36, this ASIC is connected as: | On [[iNES Mapper 036|mapper 36]], this ASIC is connected as: | ||
.--\/--. | .--\/--. | ||
NC <- |01 24| -> NC | NC <- |01 24| -> NC | ||
| Line 55: | Line 55: | ||
'------' | '------' | ||
On mapper 132: | On [[iNES Mapper 132|mapper 132]]: | ||
.--\/--. | .--\/--. | ||
(r) PRG A15 <- |01 24| -> NC | (r) PRG A15 <- |01 24| -> NC | ||
| Line 71: | Line 71: | ||
'------' | '------' | ||
On mapper 173, labeled "ITC20V8-10LP" | On [[iNES Mapper 173|mapper 173]], labeled "ITC20V8-10LP" | ||
.--\/--. | .--\/--. | ||
NC <- |01 24| -> NC | NC <- |01 24| -> NC | ||
*(r) CHR A15 <- |02 23| -> NC | |||
(r) CHR A13 <- |03 22| -> CHR A14 | (r) CHR A13 <- |03 22| -> CHR A14 | ||
GND -> |04 21| <- CPU A13 (fr) | GND -> |04 21| <- CPU A13 (fr) | ||
| Line 86: | Line 86: | ||
(fr) CPU D0 <> |12 13| <- CPU A0 (fr) | (fr) CPU D0 <> |12 13| <- CPU A0 (fr) | ||
'------' | '------' | ||
<nowiki>*</nowiki> TXC pin 2 was routed to CHR ROM pin 1 on a 28-pin package. On a UVEPROM, this is A15. However, no games were ever released using more than 32 KiB of CHR. | |||
Latest revision as of 20:53, 5 September 2018
05-00002-010: 24-pin 0.3" DIP. (Mappers 036, 132, and 173)
.--\/--.
Q2 <- |01 24| -> Q3
Q1 <- |02 23| -> Q4
Q0 <- |03 22| -> o3
i1 -> |04 21| <- CPU A13 (rn)
i0 -> |05 20| <- CPU A14 (rn)
io2 <> |06 19| -- GND
5V -- |07 18| <- CPU R/W (n)
D5 <> |08 17| <- /ROMSEL (rn)
D4 <> |09 16| <- M2 (n)
D2 <> |10 15| <- CPU A8 (rn)
D1 <> |11 14| <- CPU A1 (rn)
D0 <> |12 13| <- CPU A0 (rn)
'------'
There is a lot more functionality here than was used in any of the three mappers that used it.
Mask: $E103
Write $4103: [.... ...C] - Set/Clear Increment Mode
Write $4101: [.... ...V] - Set/Clear Invert Mode. Also affects io2 and o3.
When clear, io2 relays i0. When set, io2 relays i1.
o3 is io2 OR D5 continuously.
If something externally overpowers io2, then:
When V is clear, o3 is i0 OR D5.
When V is set, o3 is io2 OR D5.
Write $4102: [..RR .PPP] - D[5,4] -> R[5,4]. D[2,1,0] -> P[2,1,0]
P3 XOR V -> P3.
Write $4100: [.... ....] - If Increment Mode is set, R[3,2,1,0] += 1
Otherwise, P[3,2,1,0] XOR V -> R[3,2,1,0]
Mask: $E100
Read $4100: [..RR .RRR] - R[5,4] XOR V -> D[5,4]. R[2,1,0] -> D[2,1,0]
Mask: $8000
Write $8000: [.... ....] - R[3,2,1,0] -> Q[3,2,1,0]. R4 XOR V -> Q4.
On mapper 36, this ASIC is connected as:
.--\/--.
NC <- |01 24| -> NC
(r) PRG A16 <- |02 23| -> NC
(r) PRG A15 <- |03 22| -> NC
GND -> |04 21| <- CPU A13 (rn)
5V -> |05 20| <- CPU A14 (rn)
NC <> |06 19| -- GND
5V -- |07 18| <- CPU R/W (n)
NC <> |08 17| <- /ROMSEL (rn)
NC <> |09 16| <- M2 (n)
NC <> |10 15| <- CPU A8 (rn)
(rn) CPU D5 <> |11 14| <- CPU A1 (rn)
(rn) CPU D4 <> |12 13| <- CPU A0 (rn)
'------'
On mapper 132:
.--\/--.
(r) PRG A15 <- |01 24| -> NC
(r) CHR A14 <- |02 23| -> NC
(r) CHR A13 <- |03 22| -> NC
GND -> |04 21| <- CPU A13 (fr)
5V -> |05 20| <- CPU A14 (fr)
NC <> |06 19| -- GND
5V -- |07 18| <- CPU R/W (f)
GND <> |08 17| <- /ROMSEL (fr)
(fr) CPU D3 <> |09 16| <- M2 (f)
(fr) CPU D2 <> |10 15| <- CPU A8 (fr)
(fr) CPU D1 <> |11 14| <- CPU A1 (fr)
(fr) CPU D0 <> |12 13| <- CPU A0 (fr)
'------'
On mapper 173, labeled "ITC20V8-10LP"
.--\/--.
NC <- |01 24| -> NC
*(r) CHR A15 <- |02 23| -> NC
(r) CHR A13 <- |03 22| -> CHR A14
GND -> |04 21| <- CPU A13 (fr)
5V -> |05 20| <- CPU A14 (fr)
NC <> |06 19| <- GND
5V -- |07 18| <- CPU R/W (f)
GND <> |08 17| <- /ROMSEL (fr)
(fr) CPU D3 <> |09 16| <- M2 (f)
(fr) CPU D2 <> |10 15| <- CPU A8 (fr)
(fr) CPU D1 <> |11 14| <- CPU A1 (fr)
(fr) CPU D0 <> |12 13| <- CPU A0 (fr)
'------'
* TXC pin 2 was routed to CHR ROM pin 1 on a 28-pin package. On a UVEPROM, this is A15. However, no games were ever released using more than 32 KiB of CHR.
