Talk:APU Noise: Difference between revisions
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Curiously, the noise channel's frequency counter [http://uxul.org/~noname/chips/cpu-2/no-metal/stitched/final/ on the die] isn't an ordinary counter - it's an '''11-bit linear feedback shift register''' (with taps at the 9th and 11th bits); when I take the counter values from the on-die ROM and run the LFSR until the result is '10000000000', the cycle counts (for NTSC) match once multiplied by 2 (note that this means the PAL frequency for $1 is almost definitely wrong). --[[User:Quietust|Quietust]] 04:58, 23 January 2011 (UTC) | Curiously, the noise channel's frequency counter [http://uxul.org/~noname/chips/cpu-2/no-metal/stitched/final/ on the die] isn't an ordinary counter - it's an '''11-bit linear feedback shift register''' (with taps at the 9th and 11th bits); when I take the counter values from the on-die ROM and run the LFSR until the result is '10000000000', the cycle counts (for NTSC) match once multiplied by 2 (note that this means the PAL frequency for $1 is almost definitely wrong). --[[User:Quietust|Quietust]] 04:58, 23 January 2011 (UTC) | ||
"randomly 93 or 31 steps long otherwise. (The particular 31- or 93-step sequence depends on where in the 32767-step sequence the shift register was when Mode flag was set" - seems worth mentioning that, while random, there is only one 31 step pattern [1101000100101011000011100110111], and it occurs 1/1057 of the time. This compares to the 352 different 93 step patterns that occur the other 1056/1057 of the time. | |||
Revision as of 15:05, 17 April 2021
Curiously, the noise channel's frequency counter on the die isn't an ordinary counter - it's an 11-bit linear feedback shift register (with taps at the 9th and 11th bits); when I take the counter values from the on-die ROM and run the LFSR until the result is '10000000000', the cycle counts (for NTSC) match once multiplied by 2 (note that this means the PAL frequency for $1 is almost definitely wrong). --Quietust 04:58, 23 January 2011 (UTC) "randomly 93 or 31 steps long otherwise. (The particular 31- or 93-step sequence depends on where in the 32767-step sequence the shift register was when Mode flag was set" - seems worth mentioning that, while random, there is only one 31 step pattern [1101000100101011000011100110111], and it occurs 1/1057 of the time. This compares to the 352 different 93 step patterns that occur the other 1056/1057 of the time.
