Talk:CPU pinout: Difference between revisions
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m (figured out the part that goes to M2 - it's merged with /RESET) |
m (traced enough of it to determine this - if both /RESET and pin 30 are low, then the output drivers for M2 will be disabled and the pin will float) |
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==Pin 30== | ==Pin 30== | ||
The signal from pin 30 goes through the exact same "processing" as the chip's /RESET signal, at which point it goes to the output logic for the M2 pin (don't know exactly what it does) and then through an inverter which goes to the enables for $4018-$401A and to some other spots (seemingly related to the data buffer used for Sprite DMA). Bit 7 of the writable register at $401A seems to propagate to numerous locations within the sound channels and thus might be responsible for the observation of all writable registers disappearing. --[[User:Quietust|Quietust]] 16:49, 29 April 2011 (UTC) | The signal from pin 30 goes through the exact same "processing" as the chip's /RESET signal, at which point it goes to the output logic for the M2 pin (don't know exactly what it does) and then through an inverter which goes to the enables for $4018-$401A and to some other spots (seemingly related to the data buffer used for Sprite DMA). Bit 7 of the writable register at $401A seems to propagate to numerous locations within the sound channels and thus might be responsible for the observation of all writable registers disappearing. --[[User:Quietust|Quietust]] 16:49, 29 April 2011 (UTC) | ||
:When pin 30's input is "processed" it gets inverted, just like with the /RESET pin (since transistors themselves are active-high) - that signal then gets inverted again (so it's now equal to pin 30's input, normalized) and NORed together with the inverted +RESET signal (so it's also the actual state of the input signal), and that result goes to the M2 pin's output logic; thus, | :When pin 30's input is "processed" it gets inverted, just like with the /RESET pin (since transistors themselves are active-high) - that signal then gets inverted again (so it's now equal to pin 30's input, normalized) and NORed together with the inverted +RESET signal (so it's also the actual state of the input signal), and that result goes to the M2 pin's output logic; thus, if pin 30 is pulled high, then M2 will '''not''' be tri-stated during RESET. --[[User:Quietust|Quietust]] 20:33, 7 May 2011 (UTC) | ||
Revision as of 20:33, 7 May 2011
Pin 30
The signal from pin 30 goes through the exact same "processing" as the chip's /RESET signal, at which point it goes to the output logic for the M2 pin (don't know exactly what it does) and then through an inverter which goes to the enables for $4018-$401A and to some other spots (seemingly related to the data buffer used for Sprite DMA). Bit 7 of the writable register at $401A seems to propagate to numerous locations within the sound channels and thus might be responsible for the observation of all writable registers disappearing. --Quietust 16:49, 29 April 2011 (UTC)
- When pin 30's input is "processed" it gets inverted, just like with the /RESET pin (since transistors themselves are active-high) - that signal then gets inverted again (so it's now equal to pin 30's input, normalized) and NORed together with the inverted +RESET signal (so it's also the actual state of the input signal), and that result goes to the M2 pin's output logic; thus, if pin 30 is pulled high, then M2 will not be tri-stated during RESET. --Quietust 20:33, 7 May 2011 (UTC)
