Talk:MMC3

The hardware section of this page needs to be tidied up a bit, because right now, it's just a giant infodump with little organization. :P --Drag 13:09, 4 June 2012 (PDT)

There's some documentation about the differences between MMC3 revisions here: [1] I'll add them in at some point, if nobody else does. --Drag 18:00, 19 April 2011 (UTC)

PRG RAM bank behavior

When PRG RAM is accessed via $6000-$7FFF, what does the MMC3 put on the upper PRG ROM address lines? --Tepples 23:24, 20 April 2011 (UTC)

Ideally, the MMC3 wouldn't put anything on the ROM address lines. :P Either way, if the CPU is accessing $6000-7FFF, I'd imagine whatever chip is selected would see %011xxxxx xxxxxxxx on its address lines. RAM would just see the x part, and whatever mapper-supplemented upper address lines if the RAM is bankswitched. --Drag 04:05, 21 April 2011 (UTC)

When I hear "wouldn't put anything", I think "high impedance". It appears you claim that if $6000-$7FFF is accessed, the PRG A13 through PRG A18 outputs from the mapper are high-Z, not the value in either PRG bank register. Do I misunderstand? --Tepples 22:42, 21 April 2011 (UTC)

The simplest thing electrically is to never disable the address drivers. Given how MMC3 works I'd guess it drives the upper address lines high. Lidnariq 18:08, 22 April 2011 (UTC)

Actually, I'm not entirely sure I understand what you're saying. When you say PRG ROM address lines, I thought you meant the address lines on the actual ROM. Yes, even if the CPU is accessing $6000-7FFF, the ROM would still see the address bus, but it won't do anything with it, because the mapper won't select the chip. That's what I meant by "wouldn't put anything on the ROM address lines". Even though it's physically putting something there, the ROM is disabled so it never does anything with it.

If you're talking about what happens with WRAM, I imagine the chip wouldn't have the upper three address lines, unless the RAM is bankswitched. --Drag 07:33, 25 April 2011 (UTC)

I was asking whether or not it's feasible to build PRG RAM bankswitching by running the same upper address lines out of the mapper to both PRG ROM and PRG RAM. When PRG RAM is being accessed, what is the voltage on each of the upper address lines PRG A18-A13 (pins 23, 25, 21, 18, 22, 19) coming out of the MMC3? Does it depend on either of the PRG ROM bank values, or is it a constant value? --Tepples 13:25, 25 April 2011 (UTC)

Ahh, ok, that makes more sense. The MMC3 outputs different things to the most significant rom bits depending on what address is being accessed, so it's entirely possible that the circuitry involved selects between a couple different latches, depending on bits 14 and 13 of the PRG address. If it uses an ordinary decoder, then it's possible that bit 15 goes to the /OE of whatever multiplexer it uses.

TL;DR: The "banks" for $0000-$7FFF may mirror the bank configuration of $8000-$FFFF, or it may not. Either way, accessing $6000-7FFF is like accessing $E000-FFFF (which is fixed to the last bank), so whether it looks at A15 or not, you'll probably end up with all 1's across A13+. This is just my speculation though. --Drag 19:56, 25 April 2011 (UTC)

I can't say for sure, because very complex equipment would be needed to verify this, but it's extremely likely that the MMC3's PRG-banking ciruitery completely ignores the state of A15. That is, acessing any adress with A15 low will have the higher adress lines pointed to the same latch as if the corresponding adress with A15 high was used. In particular, when acessing $6000-$7fff, the MMC3 will act like when acessing $e000-$ffff (which means all adress lines will go high, pointing to the "last-hardwired" bank).

This hypothesis is especially robust when you consider there is no A15 on the cart edge, so you have to invert PRG /CE to get the state of A15. Also, when the PPU fetches nametable area ($2000-$2fff), the MMC3 does bank the CHR-ROM exactly like when acessing the corresponding area with A13 low, that is $0000-$1fff, and the TLSROM and TKSROM boards makes a good use of this.

This is valid not only for the MMC3 but for 99% of mappers in fact : Anyone would be crazy to add extra circuitry in their chips so that it acts differently when the CPU is adressing space where the ROM will never respond anyways. (Probably only mappers such as the MMC5 or FME7, which can map ROM and RAM anywhere regardless of the state of A15, will not follow this rule). So, no, sorry but no PRG-RAM switching would be possible on MMC3. But any mapper that was not designed to switch PRG-RAM, but that was designed to switch PRG-ROM at $e000-$ffff could be abused to also switch RAM. Bregalad 11:39, 1 May 2011 (UTC)

What happens when both background and sprites are fetched from $1xxx? --Zepper 02:28, 8 November 2011 (UTC)

The MMC3 scanline counter is based entirely on PPU A12, triggered on rising edges (after the line remains low for a sufficiently long period of time) Which period of time exactly?