User:NewRisingSun/VTxx
New Features
V.R. Technology's NES-on-a-chip consoles enhance the original NES/Famicom in several aspects. In this description, features are assigned to the earliest console type for which a datasheet is publicly available. The publicly-available datasheets are for the VT01, VT02, VT03, VT16 and VT18. Therefore, a feature described as VT16+ may have been available earlier on VT04 to VT15 consoles.
VT02+ Features
- OneBus mode: PRG and CHR data come from the same address space. The cartridge connector's PPU Address lines are repurposed as higher-order Address lines.
- Integrated MMC3-compatible bankswitching by the console, active when in OneBus mode.
- Ability to use NTRAM as CHR-RAM.
- Choice of A12 and HBLANK as a source for clocking the scanline interrupt.
- Automatic X/Y light gun position determination.
- Integrated RS232 interface.
- Direct NTSC/PAL and 50/60 Hz identification.
- Automatic per-attribute-tile background and per-sprite sprite bankswitching.
- DMA can be used to transfer data to PPU memory (via $2007) in addition to the normal transferring of data to OAM memory (via $2004).
- A second APU doubling the number of sound channels.
- Raw PCM output using full eight bits of resolution.
- DMA-driven raw PCM output.
- Data for DMA-driven DPCM/PCM output can be placed anywhere in CPU address space, not just within the $C000-$FFFF range.
VT03+ Features
- Sprites can be 16 pixels wide.
- Graphics can use four bits-per-pixel, so that together with two attribute data bits, sixty-four rather than 16 colors each for background and sprites may be chosen.
- Enhanced color palette with twelve bits rather than six bits per color.
VT16+ Features
- Internal CPU RAM is 4 KiB rather than just 2 KiB.
- The CPU can be set to run at the same speed (5.37 MHz) as the PPU.
- The CPU can be set to retrieve interrupt vectors from RAM ($0FFx) rather than ROM ($FFFx).
- DMA-driven DPCM/PCM output can be set to use its own banking registers independent of normal PRG banking.
- Hardware random number generator.
Memory Map
CPU Memory Map
CPU $0000-$07FF: 2 KiB of internal RAM CPU $0800-$0FFF: VT16+: VT01-VT03: Mirror of CPU $0000-$07FF, VT16+: Further 2 KiB of internal RAM CPU $1000-$1FFF: Mirror of CPU $0000-$0FFF CPU $2000-$2007: RP2C02-compatible PPU registers CPU $2010-$201F: New PPU registers CPU $4000-$401F: RP2A03-compatible APU, DMA and I/O registers CPU $4020-$403F: New APU, DMA and I/O registers CPU $4100-$41FF: New miscellaneous registers CPU $6000-$7FFF: Optional WRAM, if present on cartridge CPU $8000-$FFFF (write): When forwarding is enabled (register $410B bit 3 "FWEN" =0): MMC3-compatible registers that are forwarded to $4101-$4108) CPU $8000-$FFFF (read): Four 8 KiB PRG-ROM banks. See the section "PRG-ROM Bankswitching" for details.
PPU Memory Map
PPU $0000-$1FFF: CHR-ROM, all modes: CHR pattern data, bit planes 0 and 1
PPU $2000-$2FFF: NTRAM (2 KiB, selectable mirroring)
PPU $3F00-$3F1F: CGRAM in two bits per color modes, entries $3F10/$3F14/$3F18/$3F01 mirrors of $3F00/$3F04/$3F08/$3F0C.
VT03+: Also CGRAM in four bits per color modes, bits 0 to 5, of colors 00-1F; same mirroring of address bit 4 applies.
PPU $3F20-$3F7F: VT03+: CGRAM in four bits per color modes, bits 0 to 5, of colors 20-7F; no mirroring of address bit 4.
PPU $3F80-$3FFF: VT03+: CGRAM in four bits per color modes, bits 6 to 11, of colors 00-7F; no mirroring of address bit 4.
PPU $4000-$5FFF: CHR-ROM, 4 bits per pixel modes: CHR pattern data, bit planes 2 and 3 (VT03+)
PRG-ROM Bankswitching
The bankswitching scheme is based on, and indeed backwards-compatible to, the Nintendo MMC3's. The CPU address range is divided into four 8 KiB banks. For each of these four 8 KiB banks, the bank number is made up of four components:
- an Inner Bank that resembles the MMC3's bank registers,
- a Middle Bank that can replace zero to eight bits of the lower bank number,
- an Outer Bank that extend the address range up to 32 MiB.
- a Relative Bank that adds a fixed value to the previous three components (VT16+ only).
The final 8 KiB PRG-ROM bank number therefore is:
BankNumber = ((InnerBank &InnerBankMask) | (MiddleBank &~InnerBankMask) | (OuterBank <<8)) +RelativeBank;
Inner PRG Bank number
The lower bits bits of the 8 KiB PRG-ROM bank number, constituting the Inner Bank number, are normally the only ones that are manipulated by individual games. By default, they resemble the MMC3's original bank registers; accordingly, two of the four banks are fixed. By setting bit 6 in register $410B (PQ2EN), the $C000-$DFFF bank may be turned into a selectable bank as well.
CPU $8000-$9FFF: Selected by register $4107 (PQ0), akin to MMC3 register 6.
CPU $A000-$BFFF: Selected by register $4108 (PQ1), akin to MMC3 register 7.
CPU $C000-$DFFF: If $410B bit 6 (PQ2EN)=0: Fixed to $FE, or second-to-last bank (within the Middle/Outer Bank), as on the MMC3.
If $410B bit 6 (PQ2EN)=1: Selected by register $4109 (PQ2), an enhancement over the MMC3.
CPU $E000-$FFFF: Fixed to $FF, or last bank (within the Middle/Outer Bank), as on the MMC3.
If $4105 bit 6 (COMR6) is 1, then the sources of the $8000-$9FFF/$A000-$BFFF bank numbers are swapped with the $C000-$DFFF/$E000-$FFFF banks', just as on the MMC3, or in other words, CPU A14 is inverted.
Middle PRG Bank mask and number
The Middle Bank is normally only used on multicarts. It allows masking off and replacing bits of the Inner Bank number, so that several games may be put into one Outer Bank. Bits 0-2 of register $410B (PS) select the AND mask that is applied to the Inner Bank number. Only the bits that have been masked off that way are then replaced with the respective bits from register $410A (PQ3):
$410B Inner Bank Middle Bank Effective bits 0-2 AND Mask AND Mask Inner Bank Size -------- ---------- -------- --------------- 0 3F C0 512 KiB 1 1F E0 256 KiB 2 0F F0 128 KiB 3 07 F8 64 KiB 4 03 FC 32 KiB 5 01 FE 16 KiB 6 00 FF 8 KiB 7 FF 00 2048 KiB
Outer PRG Bank number
The Outer Bank number is used mostly by multicarts, but also by very large games for which the maximum Inner Bank size of 2 MiB is insufficient. On the VT02 and VT03, bits 4-7 of register $4100 simply select the 2 MiB Outer Bank number for all four banks. On the VT16+, if register $411C bit 5 (EXT2421EN) is set, each of the four 8 KiB banks in the CPU $8000-$FFFF address range can have its own Outer Bank number.
VT02, VT03; VT16+ with $411C bit 5 (EXT2421)=0:
CPU $8000-$FFFF: Selected by register $4100 bits 4-7 (PQ7).
VT16+ with $411C bit 6 (EXT2421)=1:
CPU $8000-$9FFF: Selected by register $4110 bits 0-3 (PQ4).
CPU $A000-$BFFF: Selected by register $4110 bits 4-7 (PQ5).
CPU $C000-$DFFF: If $410B bit 6 (PQ2EN)=0: Selected by $4100 bits 4-7 (PQ7), as on VT02/VT03.
If $410B bit 6 (PQ2EN)=1: Selected by $4111 bits 0-3 (PQ6).
CPU $E000-$FFFF: Selected by $4100 bits 4-7 (PQ7), as on VT02/VT03.
If $4105 bit 6 (COMR6) is 1, then the sources of the $8000-$9FFF/$A000-$BFFF bank numbers are swapped with the $C000-$DFFF/$E000-$FFFF banks', as was the case with the Inner Bank number.
Relative Bank number
The Relative Bank only exists on the VT16 and later consoles. While Inner, Middle and Outer Bank numbers are combined with AND and OR operations, the Relative Bank is simply added, yielding much greater flexibility. The Relative Bank Number is defined by registers $4127 (bits 0-7) and $4128 (bits 0-2), yielding 11 bits. Because the Relative Bank number has only eleven rather than the twelve bits of the combined Inner, Middle and Outer Bank numbers, it is guaranteed that final bank number does not overflow within the defined address space, guaranteeing forward-compatibility with future revisions of the console that may extend the address space.
CHR-ROM Layout
The layout of CHR-ROM, and by consequence the meaning of the CHR bank registers, is dependent on the current video mode. The concept of a video mode is rarely applied to the original NES/Famicom, as it would be considered to only have a single one. Things are more complex on the VTxx series: the VT02 has two, the VT03 has four, and the VT16+ have six video modes defined by the number of bits per pixel, whether Address Extension is used, and whether the Video Data Bus has eight or sixteen bits:
| Bits per pixel | Address Extension | Video Data Bus Width | |
|---|---|---|---|
| 8 bit | 16 bit | ||
| 2 | off | RP2C02+ | - |
| on | VT02+ | - | |
| 4 | off | VT03 | VT16+ |
| on | VT03+ | VT16+ | |
Bits per pixel
The number of bits per pixel is selected separately for background and sprites. For background, the two additional bits are always used to form four-bit color numbers. For sprites in four bits per pixel modes, it can further be selected whether the second pair of bits is to be used to form a four-bit color number, or whether they are used to increase the number of horizontal pixels per sprite from eight to sixteen. For the background, the number of bits per pixel is selected by register $2010 bit 1 (BK16EN), for sprites by register $2010 bit 2 (SP16EN), with a cleared bit indicating two bits per pixel, and a set bit indicating four bits per pixel.
On the VT03, the choice between sixteen colors per sprite --- register $2010 bit 0 (PIX16EN) cleared --- and sixteen pixels per sprite --- register $2010 bit 0 (PIX16EN) set --- applies to all sprites. On the VT16+, the same applies if register $2010 bit 5 (SPOPEN) is cleared; if register $2010 bit 2 (SP16EN) and bit 5 (SPOPEN) are both set, the choice can be made for each sprite individually by clearing (sixteen colors) or setting (sixteen pixels) bit 4 of byte 2 of that sprite's OAM data.
Address Extension
On the original NES/Famicom, both background and sprite tiles are indexed by an eight-bit number taken from the nametable for backgrounds and byte 1 of each sprites' OAM data. This concept is kept on the VTxx series if Address Extension is disabled. Address Extension can be enabled separately for background --- by setting register $2010 bit 4 (BKEXTEN) --- and sprite data --- by setting register $2010 bit 3 (SPEXTEN). Address Extension extends the tile number to eleven bits, which can be seen as performing an implicit bankswitch for each tile.
If Address Extension is enabled for background data, then the tile number is extended to eleven bits, with bits 8 and 9 taken from that tile's respective attribute table entry. The source of bit 10 is selected by register $2011 bit 0 (EVA12S): if it is cleared, then register $2018 bit 3 (BKPAGE) is used; if it is set, the current Mirroring setting is taken from register $4106 bit 0 (H/V Mirroring). Since the two bits from the attribute table are now used as part of the tile number, they are forced to zero when forming the final palette index of each pixel. Since this effectively reduces the number of available background colors by a factor of four, background address extension is only used in games using four bits per pixel modes. VR Technology's VT03 Demonstration ROM image uses Background Address Extension to show off the use of many Chinese characters on a single page.
If Address Extension is enabled for sprite data, then the tile number is extended to eleven bits by using bits 2-4 of each sprite's PPU OAM byte 2, which were unused on the original NES/Famicom, as tile number bits 8-10. The number of available colors is not reduced. Note that on the VT16+ with register $2010 bit 2 (SP16EN) and bit 5 (SPOPEN) both set, each sprite's PPU OAM byte 2 bit 4 is also used to choose between sixteen colors and sixteen pixels.
Note that if Address Extension is enabled for either background or sprite data, it is automatically enabled when accessing CHR data from the CPU via PPU register $2007 as well.
CHR Pattern Data Layout
In two bits per pixel modes, each CHR data layout is the same as on the original NES/Famicom, with each tile's CHR data occupying sixteen bytes, and the two bitplanes' data stored sequentially:
Byte Bit Meaning Byte Bit Meaning ---------------- ---------------- 0 7 pixel Y=0 X=0, bit 0 8 7 pixel Y=0 X=0, bit 1 0 6 pixel Y=0 X=1, bit 0 8 6 pixel Y=0 X=1, bit 1 0 5 pixel Y=0 X=2, bit 0 8 5 pixel Y=0 X=2, bit 1 0 4 pixel Y=0 X=3, bit 0 8 4 pixel Y=0 X=3, bit 1 0 3 pixel Y=0 X=4, bit 0 8 3 pixel Y=0 X=4, bit 1 0 2 pixel Y=0 X=5, bit 0 8 2 pixel Y=0 X=5, bit 1 0 1 pixel Y=0 X=6, bit 0 8 1 pixel Y=0 X=6, bit 1 0 0 pixel Y=0 X=7, bit 0 8 0 pixel Y=0 X=7, bit 1 1 7 pixel Y=1 X=0, bit 0 9 7 pixel Y=1 X=0, bit 1 1 6 pixel Y=1 X=1, bit 0 9 6 pixel Y=1 X=1, bit 1 1 5 pixel Y=1 X=2, bit 0 9 5 pixel Y=1 X=2, bit 1 1 4 pixel Y=1 X=3, bit 0 9 4 pixel Y=1 X=3, bit 1 1 3 pixel Y=1 X=4, bit 0 9 3 pixel Y=1 X=4, bit 1 1 2 pixel Y=1 X=5, bit 0 9 2 pixel Y=1 X=5, bit 1 1 1 pixel Y=1 X=6, bit 0 9 1 pixel Y=1 X=6, bit 1 1 0 pixel Y=1 X=7, bit 0 9 0 pixel Y=1 X=7, bit 1 2 7 pixel Y=2 X=0, bit 0 A 7 pixel Y=2 X=0, bit 1 : : : : : : 7 7 pixel Y=7 X=7, bit 0 F 7 pixel Y=7 X=7, bit 1 All numbers hexadecimal.
In the four bits per pixel with 8 bit data bus modes, the same plane-sequential system is expanded, so that each tile's CHR data now occupies thirty-two bytes:
Byte Bit Meaning Byte Bit Meaning Byte Bit Meaning Byte Bit Meaning ---------------- ---------------- ---------------- ---------------- 00 7 pixel Y=0 X=0, bit 0 08 7 pixel Y=0 X=0, bit 1 10 7 pixel Y=0 X=0, bit 2 18 7 pixel Y=0 X=0, bit 3 00 6 pixel Y=0 X=1, bit 0 08 6 pixel Y=0 X=1, bit 1 10 6 pixel Y=0 X=1, bit 2 18 6 pixel Y=0 X=1, bit 3 00 5 pixel Y=0 X=2, bit 0 08 5 pixel Y=0 X=2, bit 1 10 5 pixel Y=0 X=2, bit 2 18 5 pixel Y=0 X=2, bit 3 00 4 pixel Y=0 X=3, bit 0 08 4 pixel Y=0 X=3, bit 1 10 4 pixel Y=0 X=3, bit 2 18 4 pixel Y=0 X=3, bit 3 00 3 pixel Y=0 X=4, bit 0 08 3 pixel Y=0 X=4, bit 1 10 3 pixel Y=0 X=4, bit 2 18 3 pixel Y=0 X=4, bit 3 00 2 pixel Y=0 X=5, bit 0 08 2 pixel Y=0 X=5, bit 1 10 2 pixel Y=0 X=5, bit 2 18 2 pixel Y=0 X=5, bit 3 00 1 pixel Y=0 X=6, bit 0 08 1 pixel Y=0 X=6, bit 1 10 1 pixel Y=0 X=6, bit 2 18 1 pixel Y=0 X=6, bit 3 00 0 pixel Y=0 X=7, bit 0 08 0 pixel Y=0 X=7, bit 1 10 0 pixel Y=0 X=7, bit 2 18 0 pixel Y=0 X=7, bit 3 01 7 pixel Y=1 X=0, bit 0 09 7 pixel Y=1 X=0, bit 1 11 7 pixel Y=1 X=0, bit 2 19 7 pixel Y=1 X=0, bit 3 01 6 pixel Y=1 X=1, bit 0 09 6 pixel Y=1 X=1, bit 1 11 6 pixel Y=1 X=1, bit 2 19 6 pixel Y=1 X=1, bit 3 01 5 pixel Y=1 X=2, bit 0 09 5 pixel Y=1 X=2, bit 1 11 5 pixel Y=1 X=2, bit 2 19 5 pixel Y=1 X=2, bit 3 01 4 pixel Y=1 X=3, bit 0 09 4 pixel Y=1 X=3, bit 1 11 4 pixel Y=1 X=3, bit 2 19 4 pixel Y=1 X=3, bit 3 01 3 pixel Y=1 X=4, bit 0 09 3 pixel Y=1 X=4, bit 1 11 3 pixel Y=1 X=4, bit 2 19 3 pixel Y=1 X=4, bit 3 01 2 pixel Y=1 X=5, bit 0 09 2 pixel Y=1 X=5, bit 1 11 2 pixel Y=1 X=5, bit 2 19 2 pixel Y=1 X=5, bit 3 01 1 pixel Y=1 X=6, bit 0 09 1 pixel Y=1 X=6, bit 1 11 1 pixel Y=1 X=6, bit 2 19 1 pixel Y=1 X=6, bit 3 01 0 pixel Y=1 X=7, bit 0 09 0 pixel Y=1 X=7, bit 1 11 0 pixel Y=1 X=7, bit 2 19 0 pixel Y=1 X=7, bit 3 02 7 pixel Y=2 X=0, bit 0 0A 7 pixel Y=2 X=0, bit 1 12 7 pixel Y=2 X=0, bit 2 1A 7 pixel Y=2 X=0, bit 3 : : : : : : : : : : : : 07 7 pixel Y=7 X=7, bit 0 0F 7 pixel Y=7 X=7, bit 1 17 7 pixel Y=7 X=7, bit 2 1F 7 pixel Y=7 X=7, bit 3 All numbers hexadecimal.
In the four bits per pixel with 16 bit data bus modes, the layout is changed towards a scheme that allows the second byte to be fetched in one 16 bit read operation:
Byte Bit Meaning Byte Bit Meaning ------------------ ------------------ 00/01 F pixel Y=0 X=0, bit 2 10/11 F pixel Y=0 X=0, bit 3 00/01 E pixel Y=0 X=1, bit 2 10/11 E pixel Y=0 X=1, bit 3 00/01 D pixel Y=0 X=2, bit 2 10/11 D pixel Y=0 X=2, bit 3 00/01 C pixel Y=0 X=3, bit 2 10/11 C pixel Y=0 X=3, bit 3 00/01 B pixel Y=0 X=4, bit 2 10/11 B pixel Y=0 X=4, bit 3 00/01 A pixel Y=0 X=5, bit 2 10/11 A pixel Y=0 X=5, bit 3 00/01 9 pixel Y=0 X=6, bit 2 10/11 9 pixel Y=0 X=6, bit 3 00/01 8 pixel Y=0 X=7, bit 2 10/11 8 pixel Y=0 X=7, bit 3 00/01 7 pixel Y=0 X=0, bit 0 10/11 7 pixel Y=0 X=0, bit 1 00/01 6 pixel Y=0 X=1, bit 0 10/11 6 pixel Y=0 X=1, bit 1 00/01 5 pixel Y=0 X=2, bit 0 10/11 5 pixel Y=0 X=2, bit 1 00/01 4 pixel Y=0 X=3, bit 0 10/11 4 pixel Y=0 X=3, bit 1 00/01 3 pixel Y=0 X=4, bit 0 10/11 3 pixel Y=0 X=4, bit 1 00/01 2 pixel Y=0 X=5, bit 0 10/11 2 pixel Y=0 X=5, bit 1 00/01 1 pixel Y=0 X=6, bit 0 10/11 1 pixel Y=0 X=6, bit 1 00/01 0 pixel Y=0 X=7, bit 0 10/11 0 pixel Y=0 X=7, bit 1 02/03 F pixel Y=1 X=0, bit 2 12/13 F pixel Y=1 X=0, bit 3 02/03 E pixel Y=1 X=1, bit 2 12/13 E pixel Y=1 X=1, bit 3 02/03 D pixel Y=1 X=2, bit 2 12/13 D pixel Y=1 X=2, bit 3 02/03 C pixel Y=1 X=3, bit 2 12/13 C pixel Y=1 X=3, bit 3 02/03 B pixel Y=1 X=4, bit 2 12/13 B pixel Y=1 X=4, bit 3 02/03 A pixel Y=1 X=5, bit 2 12/13 A pixel Y=1 X=5, bit 3 02/03 9 pixel Y=1 X=6, bit 2 12/13 9 pixel Y=1 X=6, bit 3 02/03 8 pixel Y=1 X=7, bit 2 12/13 8 pixel Y=1 X=7, bit 3 02/03 7 pixel Y=1 X=0, bit 0 12/13 7 pixel Y=1 X=0, bit 1 02/03 6 pixel Y=1 X=1, bit 0 12/13 6 pixel Y=1 X=1, bit 1 02/03 5 pixel Y=1 X=2, bit 0 12/13 5 pixel Y=1 X=2, bit 1 02/03 4 pixel Y=1 X=3, bit 0 12/13 4 pixel Y=1 X=3, bit 1 02/03 3 pixel Y=1 X=4, bit 0 12/13 3 pixel Y=1 X=4, bit 1 02/03 2 pixel Y=1 X=5, bit 0 12/13 2 pixel Y=1 X=5, bit 1 02/03 1 pixel Y=1 X=6, bit 0 12/13 1 pixel Y=1 X=6, bit 1 02/03 0 pixel Y=1 X=7, bit 0 12/13 0 pixel Y=1 X=7, bit 1 : : : : : : 0E/0F 0 pixel Y=7 X=7, bit 0 1E/1F 8 pixel Y=7 X=7, bit 1 All numbers hexadecimal. Little-endian byte order.
CHR-ROM Bankswitching
CHR-ROM bankswitching is likewise an extended version of the MMC3's. The address range is divided into two 2 KiB and four 1 KiB banks, with the bank numbers always specified with 1 KiB granularity. The 1 KiB bank number is made up of five components:
- an Inner Bank that resembles the MMC3's bank registers,
- a Middle Bank that can replace zero to eight bits of the lower bank number,
- an Outer Bank that extend the address range up to 32 MiB.
- a Relative Bank that adds a fixed value to the previous three components (VT16+ only),
- an Extended Video Address in Address Extension Mode.
Inner CHR Bank number
The lower bits bits of the 8 KiB PRG-ROM bank number, constituting the Inner Bank number, are normally the only ones that are manipulated by individual games.
PPU $0000-$03FF: Selected by register $2016 (RV4) AND $FE, akin to MMC3 register 0. PPU $0400-$07FF: Selected by register $2016 (RV5) OR $01, akin to MMC3 register 0. PPU $0800-$0BFF: Selected by register $2017 (RV5) AND $FE, akin to MMC3 register 1. PPU $0C00-$0FFF: Selected by register $2017 (RV5) OR $01, akin to MMC3 register 1 PPU $1000-$13FF: Selected by register $2012 (RV0), akin to MMC3 register 2. PPU $1400-$17FF: Selected by register $2013 (RV1), akin to MMC3 register 3. PPU $1800-$1BFF: Selected by register $2014 (RV2), akin to MMC3 register 4. PPU $1C00-$1FFF: Selected by register $2015 (RV3), akin to MMC3 register 5.
If $4105 bit 7 (COMR7) is 1, then the sources of the $0000-$0FFF bank numbers are swapped with the $1000-$1FFFbanks', just as on the MMC3, or in other words, PPU A12 is inverted.
Middle CHR Bank number
The Middle Bank is normally only used on multicarts. It allows masking off and replacing bits of the Inner Bank number, so that several games may be put into one Outer Bank. Bits 0-2 of register $201A (VB0S) select the AND mask that is applied to the Inner Bank number. Only the bits that have been masked off that way are then replaced with the respective bits from register $201A bits 3-7 (RV6):
$201A Inner Bank Middle Bank Effective bits 0-2 AND Mask AND Mask Inner Bank Size -------- ---------- -------- --------------- 0 FF 00 256 KiB 1 7F 80 128 KiB 2 3F C0 64 KiB 3 invalid 4 1F E0 32 KiB 5 0F F0 16 KiB 6 07 F8 8 KiB 7 invalid
Outer PRG Bank number
The Outer Bank number is used mostly by multicarts, but also by very large games for which the maximum Inner Bank size of 2 MiB is insufficient. Unlike PRG banking, a single Outer CHR Bank number applies to all six CHR banks.
PPU $0000-$1FFF: Selected by register $4100 bits 0-3 (VA2).
