VRC2 pinout: Difference between revisions

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m (Parodius Da? more like Parodius DEL)
(revise terminology and add variants pinouts)
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The Konami [[VRC2]] and [[VRC4]] chips come in almost-identical 40-pin DIP packages :
Konami [[VRC2]] and [[VRC4]]: 0.6" 40-pin PDIP (iNES Mappers [[iNES Mapper 021|21]], [[iNES Mapper 022|22]], [[iNES Mapper 023|23]], and [[iNES Mapper 025|25]])


 
  r: connects to ROM
* (s) means this pin is shared between rom, system and NES
  f: connects to Famicom
* (r) this only connects to the ROM  
 
* (n) means this pin is connected to the NES only
* CHR : these connect to the CHR ROM
* PPU : these connect to the PPU
* PRG : these connect to the PRG ROM
* CPU : these connect to the CPU
                   .--\/--.  
                   .--\/--.  
     (n) CPU A13 -> |01  40| -- +5V
     (f) CPU A13 -> |01  40| -- +5V
     (n) CPU A14 -> |02  39| -> PRG A17 (r)
     (f) CPU A14 -> |02  39| -> PRG A17 (r)
    (s) CPU A1 -> |03  38| -> PRG A15 (r)
    (fr) CPU Ax -> |03  38| -> PRG A15 (r)
    (s) CPU A0 -> |04  37| <- CPU A12 (s)
    (fr) CPU Ay -> |04  37| <- CPU A12 (f)
     (n) PPU A12 -> |05  36| -> PRG A14 (r)
     (f) PPU A12 -> |05  36| -> PRG A14 (r)
     (n) PPU A11 -> |06  35| -> PRG A13 (r)
     (f) PPU A11 -> |06  35| -> PRG A13 (r)
     (n) PPU A10 -> |07  34| -> PRG A16 (r)
     (f) PPU A10 -> |07  34| -> PRG A16 (r)
     (r) PRG /CE <- |08  33| <- CPU D0 (s)
     (r) PRG /CE <- |08  33| <- CPU D0 (fr)
     (n) CPU R/W -> |09  32| <- CPU D1 (s)
     (f) CPU R/W -> |09  32| <- CPU D1 (fr)
     (r) CHR /CE <- |10  31| <- CPU D2 (s)
     (r) CHR /CE <- |10  31| <- CPU D2 (fr)
     (n) PPU A13 -> |11  30| <- CPU D4 (s)
     (f) PPU A13 -> |11  30| <- CPU D4 (fr)
     (n) PPU /OE -> |12  29| <- CPU D3 (s)
     (f) PPU /OE -> |12  29| <- CPU D3 (fr)
     (n) PPU A10 -> |13  28| -> CHR A17 (r)
     (f) PPU A10 -> |13  28| -> CHR A17 (r)
     (n) /ROMSEL -> |14  27| -> CHR A15 (r)
     (f) /ROMSEL -> |14  27| -> CHR A15 (r)
         (n) M2 -> |15  26| -> CHR A12 (r)
         (f) M2 -> |15  26| -> CHR A12 (r)
               ? -- |16  25| -> CHR A14 (r)
               ? -- |16  25| -> CHR A14 (r)
   VRC4 (n) /IRQ <- |17  24| -> CHR A13 (r)
   VRC4 (f) /IRQ <- |17  24| -> CHR A13 (r)
               ? -- |18  23| -> CHR A11 (r)
               ? -- |18  23| -> CHR A11 (r)
   VRC4 WRAM /CE <- |19  22| -> CHR A16 (r)
   VRC4 WRAM /CE <- |19  22| -> CHR A16 (r)
             GND -- |20  21| -> CHR A10 (r)
             GND -- |20  21| -> CHR A10 (r)
                   `------'
                   `------'
  3, 4: see below
The VRC2's pins 16-19 seem to have been [http://forums.nesdev.org/viewtopic.php?t=8569 intended for a never-seen-used EEPROM]
Konami was greatly fond of making minor variations from one game to the next, presumably to make life harder on pirates.


On the VRC2, pins 16-19 seem to have been [http://forums.nesdev.org/viewtopic.php?t=8569 intended for a never-seen-used EEPROM]
VRC4a, PCB 352398, mapper 21 submapper 9
    '''(fr) CPU A2''' -> |03  38| -> PRG A15 (r)
    '''(fr) CPU A1''' -> |04  37| <- CPU A12 (f)
VRC2c, PCB 351948, mapper 25 submapper 15 &<br/>
VRC4b, PCB 351406, mapper 25 submapper 1
    '''(fr) CPU A0''' -> |03  38| -> PRG A15 (r)
    '''(fr) CPU A1''' -> |04  37| <- CPU A12 (f)
VRC4c, PCB 352889, mapper 21 submapper 14
    '''(fr) CPU A7''' -> |03  38| -> PRG A15 (r)
    '''(fr) CPU A6''' -> |04  37| <- CPU A12 (f)
VRC4d, PCB 352400, mapper 25 submapper 3
    '''(fr) CPU A2''' -> |03  38| -> PRG A15 (r)
    '''(fr) CPU A3''' -> |04  37| <- CPU A12 (f)
VRC4e, PCB 352396, mapper 23 submapper 10
    '''(fr) CPU A3''' -> |03  38| -> PRG A15 (r)
    '''(fr) CPU A2''' -> |04  37| <- CPU A12 (f)
VRC2b, PCBs 350603, 350636, 350926, and 351179, mapper 23 submapper 15
    '''(fr) CPU A1''' -> |03  38| -> PRG A15 (r)
    '''(fr) CPU A0''' -> |04  37| <- CPU A12 (f)
VRC2a, PCB 351618, mapper 22 submapper 15
    '''(fr) CPU A0''' -> |03  38| -> PRG A15 (r)
    '''(fr) CPU A1''' -> |04  37| <- CPU A12 (f)
                  ⋮    ⋮
    (f) PPU A10 -> |13  28| -> '''CHR A16 (r)'''
    (f) /ROMSEL -> |14  27| -> '''CHR A14 (r)'''
        (f) M2 -> |15  26| -> '''CHR A11 (r)'''
              ? -- |16  25| -> '''CHR A13 (r)'''
  VRC4 (f) /IRQ <- |17  24| -> '''CHR A12 (r)'''
              ? -- |18  23| -> '''CHR A10 (r)'''
  VRC4 WRAM /CE <- |19  22| -> '''CHR A15 (r)'''
            GND -- |20  21| -> '''n/c'''

Revision as of 10:33, 29 January 2013

Konami VRC2 and VRC4: 0.6" 40-pin PDIP (iNES Mappers 21, 22, 23, and 25) 

 r: connects to ROM
 f: connects to Famicom
 
                  .--\/--. 
   (f) CPU A13 -> |01  40| -- +5V
   (f) CPU A14 -> |02  39| -> PRG A17 (r)
   (fr) CPU Ax -> |03  38| -> PRG A15 (r)
   (fr) CPU Ay -> |04  37| <- CPU A12 (f)
   (f) PPU A12 -> |05  36| -> PRG A14 (r)
   (f) PPU A11 -> |06  35| -> PRG A13 (r)
   (f) PPU A10 -> |07  34| -> PRG A16 (r)
   (r) PRG /CE <- |08  33| <- CPU D0 (fr)
   (f) CPU R/W -> |09  32| <- CPU D1 (fr)
   (r) CHR /CE <- |10  31| <- CPU D2 (fr)
   (f) PPU A13 -> |11  30| <- CPU D4 (fr)
   (f) PPU /OE -> |12  29| <- CPU D3 (fr)
   (f) PPU A10 -> |13  28| -> CHR A17 (r)
   (f) /ROMSEL -> |14  27| -> CHR A15 (r)
        (f) M2 -> |15  26| -> CHR A12 (r)
             ? -- |16  25| -> CHR A14 (r)
 VRC4 (f) /IRQ <- |17  24| -> CHR A13 (r)
             ? -- |18  23| -> CHR A11 (r)
 VRC4 WRAM /CE <- |19  22| -> CHR A16 (r)
           GND -- |20  21| -> CHR A10 (r)
                  `------'
 3, 4: see below

The VRC2's pins 16-19 seem to have been intended for a never-seen-used EEPROM

Konami was greatly fond of making minor variations from one game to the next, presumably to make life harder on pirates.

VRC4a, PCB 352398, mapper 21 submapper 9 

   (fr) CPU A2 -> |03  38| -> PRG A15 (r)
   (fr) CPU A1 -> |04  37| <- CPU A12 (f)

VRC2c, PCB 351948, mapper 25 submapper 15 &
VRC4b, PCB 351406, mapper 25 submapper 1 

   (fr) CPU A0 -> |03  38| -> PRG A15 (r)
   (fr) CPU A1 -> |04  37| <- CPU A12 (f)

VRC4c, PCB 352889, mapper 21 submapper 14 

   (fr) CPU A7 -> |03  38| -> PRG A15 (r)
   (fr) CPU A6 -> |04  37| <- CPU A12 (f)

VRC4d, PCB 352400, mapper 25 submapper 3 

   (fr) CPU A2 -> |03  38| -> PRG A15 (r)
   (fr) CPU A3 -> |04  37| <- CPU A12 (f)

VRC4e, PCB 352396, mapper 23 submapper 10 

   (fr) CPU A3 -> |03  38| -> PRG A15 (r)
   (fr) CPU A2 -> |04  37| <- CPU A12 (f)

VRC2b, PCBs 350603, 350636, 350926, and 351179, mapper 23 submapper 15 

   (fr) CPU A1 -> |03  38| -> PRG A15 (r)
   (fr) CPU A0 -> |04  37| <- CPU A12 (f)

VRC2a, PCB 351618, mapper 22 submapper 15 

   (fr) CPU A0 -> |03  38| -> PRG A15 (r)
   (fr) CPU A1 -> |04  37| <- CPU A12 (f)
                  ⋮     ⋮
   (f) PPU A10 -> |13  28| -> CHR A16 (r)
   (f) /ROMSEL -> |14  27| -> CHR A14 (r)
        (f) M2 -> |15  26| -> CHR A11 (r)
             ? -- |16  25| -> CHR A13 (r)
 VRC4 (f) /IRQ <- |17  24| -> CHR A12 (r)
             ? -- |18  23| -> CHR A10 (r)
 VRC4 WRAM /CE <- |19  22| -> CHR A15 (r)
           GND -- |20  21| -> n/c
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