VRC7 pinout: Difference between revisions

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(Traced the other VRC7 game from bootgod's DB images (Tiny Toon Adventures 2), established what those "NC" pins were for. Also added direction arrows)
(reformat to wiki pinout convention)
Line 1: Line 1:
<pre>
Konami [[VRC7]]: 48-pin 0.6" PDIP marked: "VRV VII 053982" (canonically [[iNES Mapper 085]])
Legend:
                .---\/---.
-------
    PPU /RD -> | 01 48 | -- NC
 
    PPU A13 -> | 02 47 | <- M2
(s) means this pin connects to the System
        GND -- | 03 46 | -> WRAM /CS
(r) this only connects to the ROM
        R/W -> | 04 45 | <- /ROMSEL
(w) this is a SRAM/WRAM connection only
        /IRQ <- | 05 44 | -> PRG /CS
PRG : these connect to the PRG ROM and/or fami's PRG pins
  CIRAM A10 <- | 06 43 | -> Audio Out
WRAM : this hooks to the WRAM
      CPU D0 -> | 07 42 | -- +5V
 
      CPU D1 -> | 08 41 | -> CHR A17
Note: There is a 3.58Mhz ceramic resonator connected to the "X1" and "X2"
      CPU D2 -> | 09 40 | -> CHR A16
pins.  it is the three-pin style with internal caps tied to the third pin
      CPU D3 -> | 10 39 | -> CHR A15
which is grounded.
      CPU D4 -> | 11 38 | -> CHR A14
                                 
      CPU D5 -> | 12 37 | -> CHR A13
Chip is physically marked: "VRV VII 053982"
      CPU D6 -> | 13 36 | -> CHR A12
 
      CPU D7 -> | 14 35 | -> CHR A11
                  .----\/----.
        +5V -- | 15 34 | -> CHR A10
(RAM&s) CHR /OE -> |01     48| -- NC
      CPU A5 -> | 16 33 | <- PPU A12
(RAM&s) CHR /CE -> |02     47| <- M2 (s)
  Crystal X2 -- | 17 32 | <- PPU A11
            GND -- |03     46| -> /CE WRAM (w)
  Crystal X1 -- | 18 31 | <- PPU A10
        (s) R/W -> |04     45| <- PRG /A15 (s) (aka /CE)
      CPU An -> | 19 30 | -- +5V
      (s) /IRQ <- |05     44| -> PRG ROM /CE (r)
    PRG A13 <- | 20 29 | <- CPU A14
  (s) CIRAM A11 <- |06     43| -> Audio Out
    PRG A14 <- | 21 28 | <- CPU A13
        (s) PD0 -> |07     42| -- +5V
    PRG A15 <- | 22 27 | <- CPU A12
        (s) PD1 -> |08     41| -> CHR RAM/ROM A17 (r)
    PRG A16 <- | 23 26 | -> PRG A18
        (s) PD2 -> |09     40| -> CHR RAM/ROM A16 (r)
        GND -- | 24 25 | -> PRG A17
        (s) PD3 -> |10     39| -> CHR RAM/ROM A15 (r)
                `--------'
        (s) PD4 -> |11     38| -> CHR RAM/ROM A14 (r)
 
        (s) PD5 -> |12     37| -> CHR RAM/ROM A13 (r)
  01,02: this doesn't make sense;
        (s) PD6 -> |13     36| -> CHR RAM/ROM A12 (r)
        the VRC7 provides none of hardware nametables, control of CIRAM /CE, or CHR /CE.
        (s) PD7 -> |14     35| -> CHR RAM/ROM A11 (r)
        maybe pin 48 is {pin1 OR pin2}, i.e. CHR /CE for a 28-pin CHR ROM?
            +5V -- |15     34| -> CHR RAM/ROM A10 (r)
        then why didn't TTA2 use it?
    (s) PRG A5 -> |16     33| <- CHR A12 (s)
  17,18: missing on TTA2, 3.58MHz [[wikipedia:Ceramic resonator|ceramic resonator]] on LP
    Crystal X2 -- |17     32| <- CHR A11 (s)
  19: A3 on TTA2, A4 on LP
    Crystal X1 -- |18     31| <- CHR A10 (s)
    (s) PRG A4 -> |19     30| -- +5V
(r) PRG ROM A13 <- |20     29| <- PRG A14 (s)
(r) PRG ROM A14 <- |21     28| <- PRG A13 (s)
(r) PRG ROM A15 <- |22     27| <- PRG A12 (s)
(r) PRG ROM A16 <- |23     26| -> PRG ROM A18 (r)
            GND -- |24     25| -> PRG ROM A17 (r)
                  `----------'
</pre>

Revision as of 22:47, 28 January 2013

Konami VRC7: 48-pin 0.6" PDIP marked: "VRV VII 053982" (canonically iNES Mapper 085) 

               .---\/---.
    PPU /RD -> | 01  48 | -- NC
    PPU A13 -> | 02  47 | <- M2
        GND -- | 03  46 | -> WRAM /CS
        R/W -> | 04  45 | <- /ROMSEL
       /IRQ <- | 05  44 | -> PRG /CS
  CIRAM A10 <- | 06  43 | -> Audio Out
     CPU D0 -> | 07  42 | -- +5V
     CPU D1 -> | 08  41 | -> CHR A17
     CPU D2 -> | 09  40 | -> CHR A16
     CPU D3 -> | 10  39 | -> CHR A15
     CPU D4 -> | 11  38 | -> CHR A14
     CPU D5 -> | 12  37 | -> CHR A13
     CPU D6 -> | 13  36 | -> CHR A12
     CPU D7 -> | 14  35 | -> CHR A11
        +5V -- | 15  34 | -> CHR A10
     CPU A5 -> | 16  33 | <- PPU A12
 Crystal X2 -- | 17  32 | <- PPU A11
 Crystal X1 -- | 18  31 | <- PPU A10
     CPU An -> | 19  30 | -- +5V
    PRG A13 <- | 20  29 | <- CPU A14
    PRG A14 <- | 21  28 | <- CPU A13
    PRG A15 <- | 22  27 | <- CPU A12
    PRG A16 <- | 23  26 | -> PRG A18
        GND -- | 24  25 | -> PRG A17
               `--------'
 
 01,02: this doesn't make sense; 
        the VRC7 provides none of hardware nametables, control of CIRAM /CE, or CHR /CE.
        maybe pin 48 is {pin1 OR pin2}, i.e. CHR /CE for a 28-pin CHR ROM?
        then why didn't TTA2 use it?
 17,18: missing on TTA2, 3.58MHz ceramic resonator on LP
 19: A3 on TTA2, A4 on LP
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