VRC7 pinout

Konami VRC7: 48-pin 0.6" PDIP marked: "VRC VII 053982" (canonically iNES Mapper 085)

               .---\/---.
    PPU /RD -> | 01  48 | -> NC
    PPU A13 -> | 02  47 | <- M2
        GND -- | 03  46 | -> WRAM /CS
        R/W -> | 04  45 | <- /ROMSEL
       /IRQ <- | 05  44 | -> PRG /CS
  CIRAM A10 <- | 06  43 | -> Audio Out
     CPU D0 <> | 07  42 | -- +5V
     CPU D1 <> | 08  41 | -> CHR A17
     CPU D2 <> | 09  40 | -> CHR A16
     CPU D3 <> | 10  39 | -> CHR A15
     CPU D4 <> | 11  38 | -> CHR A14
     CPU D5 <> | 12  37 | -> CHR A13
     CPU D6 <> | 13  36 | -> CHR A12
     CPU D7 <> | 14  35 | -> CHR A11
     /DEBUG -> | 15  34 | -> CHR A10
     CPU A5 -> | 16  33 | <- PPU A12
 Crystal X2 -> | 17  32 | <- PPU A11
 Crystal X1 <- | 18  31 | <- PPU A10
     CPU An -> | 19  30 | -- +5V
    PRG A13 <- | 20  29 | <- CPU A14
    PRG A14 <- | 21  28 | <- CPU A13
    PRG A15 <- | 22  27 | <- CPU A12
    PRG A16 <- | 23  26 | -> PRG A18
        GND -- | 24  25 | -> PRG A17
               `--------'
 
 01,02: this doesn't make sense; 
        the VRC7 provides none of extra nametables, control of CIRAM /CE, nor CHR /CE.
        maybe pin 48 is {pin1 OR pin2}, i.e. CHR /CE for a 28-pin CHR ROM?
        then why didn't TTA2 use it?
 17,18: missing on TTA2, 3.58MHz ceramic resonator on LP
 19: A3 on TTA2, A4 on LP

Note that "DEBUG" mode is not function compatible with the default way the VRC7 is wired; nukeykt says that “in debug mode VRC7 changes its pinout: Pin 4 -> /CS, Pin 27 -> /IC, Pin 28 -> /WE, Pin 19 -> A0. Also at least pins 2 and 47 somehow affect debug mode”

See also:

• Decap'ed VRC7: https://siliconpr0n.org/archive/doku.php?id=digshadow:konami:vrc_vii_053982
• Quietust's annotations for the above decap: http://www.qmtpro.com/~nes/chipimages/#vrc7
• More commentary on VRC7 DEBUG mode: https://siliconpr0n.org/archive/doku.php?id=vendor:yamaha:opl2#vrc7_debug_mode