CPU variants

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Beyond the well-studied 2A03G, we know of the following CPU revisions, both made by Ricoh and other manufacturers:

Official (NTSC)

All official NTSC CPUs use a ÷12 clock divider.

Part Picture First Seen Last Seen Notes
RP2A03 (ceramic) 1983-06
3G1 09
Likely similar to standard plastic RP2A03.
RP2A03 1983-07
3G2 ?7
1984-09
4J2 50
M2 duty cycle is 17/24 instead of 15/24 [1]. Lacks tonal noise mode. APU Frame Counter not restarted on reset. Has broken and disabled programmable interval timer on-die. Pin 30 connects to nothing. Other differences?
RP2A03E 1984-10
4K1 11
1986-06
6F1 23
Pin 30 is /RDY - combined with internal signals before feeding to internal 6502 +RDY.
RP2A03G 1987-04
7D3 A0
1993-11
3LM 5A
Reference model. Pin 30 enables a CPU test mode. Later runs introduced a DMC DMA bug [2].
RP2A03H 1993-12
3MM 40
1999-05
9EM 5B
No known differences from late RP2A03G.
RP2A03H (laser) 2001-03
1CL 42
2002-11
2LL 4A
RP2A04 1986-03
6C2 01
Not actually a CPU at all, just a jumper in a 40-pin PDIP. Used in place of CPUs in Vs. System boards (and thus with NTSC timing).

Official (PAL)

All official PAL CPUs use a ÷16 clock divider and they have different APU period tables than the NTSC CPUs.

Part Picture First Seen Last Seen Notes
RP2A07 1987-03
7C4 39
1990-04
0DL 2G
Input clock divider is 16. M2 duty cycle is 19/32 [3]. Changes to noise, DPCM, frame timer tables. Fixed DPCM RDY address bus glitches. Pin 30 connects to 6502 /RDY input.
RP2A07A 1991-06
1FM 3C
1992-10
2KM 3L
There are no known differences relative to 2A07letterless.

Unofficial

There are many unofficial, or "clone" CPUs. Though they generally work quite well for what they are, there are many associated quirks and quality control issues. Keep these items in mind:

  • Some clones have reversed duty cycles on the pulse channels, which causes the tone to sound different, but the pitch to remain correct.
  • All known clone CPUs use the NTSC APU period tables, including those intended for PAL systems.
  • The clock divider may be 12 (like official NTSC), 16 (like official PAL), or 15 (unique to clones) and this can be tested by dividing the master clock frequency by the observed M2 frequency.
  • If you use the incorrect clock divider, the pitch of the sound and the speed of the gameplay will be affected. See this discussion adapting to a different clock divider.
Part Clk
Div
Picture Notes
MG-N-501 ?
MG-P-501 ? Micro Genius-made clone. Die has the same (UMC) © Ⓜ B6167F marking as a UA6527P.
UA6527 12 UMC-made clone of 2A03G. Has swapped pulse channel duty cycles. Input clock Divider is 12.
UA6527P UMC-made clone of 2A03G for compatibility with NTSC software in PAL countries. Different input clock divider. Still has swapped pulse channel duty cycles. Otherwise believed same as 6527.

One revision has (UMC) © Ⓜ B6167F 1989 09 on the die.

DMC status bit is cleared 1 APU cycle later than on RP2A03 CPUs. The cause is not known. This changes the timing for DMC DMA implicit-stop glitches (the sample must be started 1 APU cycle earlier to trigger the glitches), and it is suspected that it delays DMC IRQ by 1 APU cycle. Noise channel is slightly louder than others.

16 Runs hot. Revisions without "-" in the date stamp have a ÷16 CPU divider, like 6540 and 2A07
15 Runs hot. Revisions with "-" in the date stamp and text on the bottom may have a ÷15 CPU divider.
? Runs cooler
UA6527P
(Relabeled)
Note that UA6527P chips are notorious for being other chips that were relabeled. In some cases, the chip has been sanded and relabeled, but it may still be possible to figure out what it actually is based on markings on the bottom of the chip. In other cases, the chip was painted and a new label was printed on top of that. If that's the case, the original label may be revealed by removing the paint.
Example top of a sanded, painted, and relabeled CPU. Note the level of freshness on the top side of the chip versus the generally filthy bottom side. Extrusion marks are not as deep as normal, or may be sanded away entirely.
15 This CPU has a ÷15 clock divider and correct duty cycles. These are the same bottom markings as a TA03-NP1. Pin 30 function is +TST.
15 This CPU has a ÷15 clock divider and reverse duty cycles. Pin 30 function is /RDY.
15 This CPU has a ÷15 clock divider and reverse duty cycles. Pin 30 function is /RDY.
16 This CPU has a ÷16 clock divider and reverse duty cycles.
16 This CPU has a ÷16 clock divider and reverse duty cycles. Pin 30 function is /RDY.
UA6527PQ ?
UA6540 16 UMC-made clone of 2A07 [4]. Has swapped pulse duty cycles.

Subsequent research implies this is identical to the early 6527P - NTSC tuning tables, ÷16 CPU divider. [5]

UA6547 ? Believed to be a 100% duplicate of UA6527, for use in PAL-M region.
UM6557 ? Believed to be a 100% duplicate of UA6527, for use in SECAM regions.
UM6561xx-1 12 NES-on-a-chip for NTSC. Revisions "xx" F, AF, BF, CF known.
UM6561xx-2 ? NES-on-a-chip for PAL-B. Revisions "xx" F, AF, BF, CF known.

F and AF revision pulse wave duty cycles match RP2A03, and DMC status bit is cleared 1 APU cycle later than on RP2A03 CPUs.

AF revision observed to have incorrect ASR #imm ($4B) behavior, but other stable illegal instructions work properly.

1818N ? ??-made NES-on-a-chip, NTSC timing.
T1818P ? ??-made NES-on-a-chip[[6]. Requires external 2 KiB RAMs for CPU and PPU. Swapped pulse duty cycles. DMC status bit is cleared 1 APU cycle later than on RP2A03 CPUs.
TA-03N 12

??-made die-mask clone of 2A03G. Chip underside also has two codes of currently unknown purpose. Pin 30 activates CPU Test Mode like on 2A03G. Clock Divisor is 12. Illegal opcodes are the same. Early 1991 dated chips are reported to have problems with APU DMC playback, but this was corrected in 1992 onward.
TA-03NP 15
or
12
??-made clone of 2A03G for NTSC compatibility in PAL countries. Input clock divider is 15?

But not this one, this input clock divider is 12.

TA-03NP1 15

??-made clone of 2A03G for NTSC compatibility in PAL countries. Input clock divider is 15. Fixed DPCM problems? Correct pulse channel duties. Noise channel is slightly louder than others. DMC status bit is cleared 1 APU cycle later than on RP2A03 CPUs.
PM03 ? Gradiente-made clone of 2A03G. [7]
GS87007 12 (Goldstar??)-made clone of 2A03 - has functioning decimal mode? [8]

Found in MicroGenius clone with PAL/NTSC switch.[1]

KC-6005 ? Found in MT777-DX famiclone, behaves exactly like UA6527P
6005B ?
2011 ?
“2A03E” ? Both with and without USC insignia
KP2B03E ?
6527-21 P03 15 Clock divider is /15. Pulse channel duty cycles are correct. Pin 30 is RDY.
6527 15 Clock divider is /15. Pulse channel duty cycles are correct. Pin 30 is RDY.
6527P 16 Clock divider is /16. Pulse channel duty cycles are swapped. Pin 30 is RDY.
15 Clock divider is /15. Pulse channel duty cycles are correct. Pin 30 is TEST.
HA6527P 15 Clock divider is /15. Pulse channel duty cycles are swapped. Pin 30 is RDY.
SENITON 6527P-SS-P03 15 Clock divider is /15. Pulse channel duty cycles are correct. Pin 30 is TEST.
SENITON 6527UP-8 15 Clock divider is /15. Pulse channel duty cycles are swapped. Pin 30 is RDY.
SENITON 6527AP 16 Clock divider is /16. Pulse channel duty cycles are swapped. Pin 30 is RDY.
SL/WH6527AP 15 Clock divider is /15. Pulse channel duty cycles are swapped. Pin 30 is RDY.
SNC6527P 15 Clock divider is /15. Pulse channel duty cycles are correct. Pin 30 is TEST.
XYZ-6783 ? Lacks tonal noise mode like original RP2A03, but resets APU Frame Counter on console reset like 2A03E/2A03G. Otherwise behaves like letterless RP2A03.
6538N ? ??-made CPU, despite the part number being similar to UMC PPU. Has inverted duty cycles like UA6527. DPCM works.
8Z01N 12 Found in Family Game by NTDEC.
TECH 27 15 Clock divider is /15. Pulse channel duty cycles are correct. Pin 30 is TEST.
HITEX-6527P-P03 GX 15 Clock divider is /15. Pulse channel duty cycles are correct. Pin 30 is TEST.
WDL6527P 15 Clock divider is /15. Pulse channel duty cycles are correct. Pin 30 is RDY.

If you know of other differences or other revisions, please add them!

See also