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30 October 2024
| 14:33 | PPU scrolling diffhist +247 Tepples talk contribs (→Split X/Y scroll: iProgramInCpp asked for clarification of "; ..."; Zeta suggested erring on the side of doing the third write 4 pixels early) | ||||
25 October 2024
24 October 2024
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m 19:52 | PPU registers 2 changes history +291 [Fiskbit (2×)] | |||
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19:52 (cur | prev) −23 Fiskbit talk contribs (Fixes the anchors; apparently HTML escape codes aren't acceptable.) | |||
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19:46 (cur | prev) +314 Fiskbit talk contribs (Adds anchors for old section names, to unbreak old links.) | |||
15 October 2024
| 22:36 | PPU scrolling diffhist +12 Fiskbit talk contribs (→Frequent pitfalls: Notes that PPUCTRL must also be written after using PPUADDR. Only setting PPUSCROLL is a common beginner mistake.) | ||||
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22:34 | PPU registers 2 changes history +370 [Quietust; Fiskbit] | |||
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22:34 (cur | prev) +320 Fiskbit talk contribs (→PPUADDR - VRAM address ($2006 write): Adds some more details about the high bit of t being cleared on PPUADDR 2nd write.) | ||||
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21:39 (cur | prev) +50 Quietust talk contribs (important note - bit 14 actually exists as the upper Y scroll bit, but the first write to $2006 clears it (thus necessitating the "6/5/5/6" trick)) | |||
