User contributions for Quietust

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14 July 2011

13 July 2011

12 July 2011

10 July 2011

  • 21:1421:14, 10 July 2011 diff hist −237 APU Frame Counterthere is NO 240Hz divider - the frame counter is a 15-bit counter (LFSR) that generates triggers at each cycle count; also, subtract 3 from cycle counts because of the reload delay on $4017 write

6 July 2011

30 June 2011

29 June 2011

15 June 2011

8 June 2011

6 June 2011

18 May 2011

16 May 2011

14 May 2011

11 May 2011

  • 03:1803:18, 11 May 2011 diff hist −10 File:Apu address.jpgit also overrides the noise channel's LFSR output and appears to also stop the triangle channel from being clocked; I don't know what it does to DPCM, but it's probably something similar current
  • 03:0303:03, 11 May 2011 diff hist +12 File:Apu address.jpgsetting $401A.7 prevents the square channels from outputting 0000, whether from the duty cycle generator, the sweep unit, or the length counter; the effect on triangle/noise/PCM is still unclear

10 May 2011

9 May 2011

7 May 2011

2 May 2011

29 April 2011

17 April 2011

2 April 2011

30 March 2011

20 March 2011

1 March 2011

28 February 2011

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