APU Frame Counter: Difference between revisions

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(...so misleading I made the same mistake.)
(possible purpose)
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The frame counter contains the following: [[APU Misc|divider]], looping clock [[APU Misc|sequencer]], frame interrupt flag.
The frame counter contains the following: [[APU Misc|divider]], looping clock [[APU Misc|sequencer]], frame interrupt flag.


{| border=1
{| class="tabular"
| Address || Bitfield || Description
|-
| '''$4017''' || <tt>MI--.----</tt> || '''Set mode and interrupt''' (write)
| '''$4017''' || <tt>MI--.----</tt> || '''Set mode and interrupt''' (write)
|-
|-
Line 22: Line 24:


=== Mode 0: 4-Step Sequence ===
=== Mode 0: 4-Step Sequence ===
{| border=1
{| class="tabular"
| Step || [[APU Envelope|Envelopes]] & [[APU Triangle|triangle's linear counter]] || [[APU Length Counter|Length counters]] & [[APU Sweep|sweep units]] || Frame interrupt flag
| Step || [[APU Envelope|Envelopes]] & [[APU Triangle|triangle's linear counter]] || [[APU Length Counter|Length counters]] & [[APU Sweep|sweep units]] || Frame interrupt flag
|-
|-
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| &nbsp; || ''240 Hz (approx.)'' || ''120 Hz (approx.)'' || ''60 Hz (approx.)''
| &nbsp; || ''240 Hz (approx.)'' || ''120 Hz (approx.)'' || ''60 Hz (approx.)''
|}
|}
In this mode, the interrupt flag is set every 29830 CPU cycles, which is slightly slower than the 29780.5 CPU cycles per NTSC PPU frame.
Some Nintendo arcade boards, even those not directly based on the NES, use the 2A03 CPU as a sound processor.
One of these is ''[[wikipedia:Punch-Out!! (arcade game)|Punch-Out!!]]''.
This IRQ allows the CPU to keep time even if no PPU is connected to the bus.


=== Mode 1: 5-Step Sequence ===
=== Mode 1: 5-Step Sequence ===

Revision as of 21:42, 2 April 2010

The NES APU frame counter generates low-frequency clocks for the channels and an optional 60 Hz interrupt. The name "frame counter" might be slightly misleading because the clocks have nothing to do with the video signal.

The frame counter contains the following: divider, looping clock sequencer, frame interrupt flag.

Address Bitfield Description
$4017 MI--.---- Set mode and interrupt (write)
Bit 7 M--- ---- Sequencer mode: 0 selects 4-step sequence, 1 selects 5-step sequence
Bit 6 -I-- ---- Interrupt inhibit flag. If set, the frame interrupt flag is cleared, otherwise it is unaffected.
Side effects The sequencer is restarted at step 1 of the selected mode.
If mode is 1 the sequencer is then clocked, causing the first step to be carried out immediately.
Finally, the divider is reloaded, resulting in a 1/240 second delay before the sequencer is next clocked.

The sequencer is clocked by the divider, which generates a 240 Hz (approx.) clock by dividing the master clock. The version of the CPU in NTSC and RGB systems divides the 21.47727 MHz system clock by 89490.

TODO: describe PAL

The frame interrupt flag is connected to the CPU's IRQ line.

Mode 0: 4-Step Sequence

Step Envelopes & triangle's linear counter Length counters & sweep units Frame interrupt flag
1 Clock    
2 Clock Clock  
3 Clock    
4 Clock Clock Set if interrupt inhibit is clear
  240 Hz (approx.) 120 Hz (approx.) 60 Hz (approx.)

In this mode, the interrupt flag is set every 29830 CPU cycles, which is slightly slower than the 29780.5 CPU cycles per NTSC PPU frame.

Some Nintendo arcade boards, even those not directly based on the NES, use the 2A03 CPU as a sound processor. One of these is Punch-Out!!. This IRQ allows the CPU to keep time even if no PPU is connected to the bus.

Mode 1: 5-Step Sequence

Step Envelopes & triangle's linear counter Length counters & sweep units
1 Clock Clock
2 Clock  
3 Clock Clock
4 Clock  
5    
  192 Hz (approx.), uneven timing 96 Hz (approx.), uneven timing

In this mode, the frame interrupt flag is never set.