APU Pulse: Difference between revisions

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(Make the timer description be closer to the hw reality)
(t+1 APU cycles or t+2 CPU cycles per phase)
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this timer is updated every APU cycle (i.e., every second CPU cycle), and counts ''t, t-1, ..., 0, t, t-1, ...'', clocking the waveform
this timer is updated every APU cycle (i.e., every second CPU cycle), and counts ''t, t-1, ..., 0, t, t-1, ...'', clocking the waveform
generator when it reaches 0. Since the period of the timer is ''t+1'' APU cycles and the sequencer has 8 steps, the period of the waveform is
generator when it reaches 0. Since the period of the timer is ''t+1'' APU cycles and the sequencer has 8 steps, the period of the waveform is
''8*(t+1)'' APU cycles, or equivalently ''16*(t+1)'' CPU cycles.
''8*(t+1)'' APU cycles, or equivalently ''16*(t+2)'' CPU cycles.


Hence
Hence

Revision as of 02:27, 29 April 2013

Each of the two NES APU pulse (square) wave channels generate a pulse wave with variable duty.

Each pulse channel contains the following: envelope generator, sweep unit, timer, 8-step sequencer, length counter.

                     Sweep -----> Timer
                       |            |
                       |            |
                       |            v 
                       |        Sequencer   Length Counter
                       |            |             |
                       |            |             |
                       v            v             v
    Envelope -------> Gate -----> Gate -------> Gate --->(to mixer)
Address Bitfield Description
$4000 DDle.eeee Pulse 1 duty, length counter halt, and envelope (write)
$4004 DDle.eeee Pulse 2 duty, length counter halt, and envelope (write)
bits 7-6 DD-- ---- The duty cycle is set (see table below). The sequencer's current position is not changed.
 
$4002 LLLL.LLLL Pulse 1 timer low (write)
$4006 LLLL.LLLL Pulse 2 timer low (write)
bits 7-0 LLLL LLLL Timer low 8 bits
 
$4003 llll.lHHH Pulse 1 length counter load and timer high (write)
$4007 llll.lHHH Pulse 2 length counter load and timer high (write)
bits 2-0 ---- -HHH Timer high 3 bits
Side effects The sequencer is restarted at the first value of the current sequence. The envelope is also restarted.

Duty Cycle Sequences

Duty Waveform sequence
0 0 1 0 0 0 0 0 0 (12.5%)
1 0 1 1 0 0 0 0 0 (25%)
2 0 1 1 1 1 0 0 0 (50%)
3 1 0 0 1 1 1 1 1 (25% negated)
The reason for these odd sequences is that the sequence counter is initialized to zero but counts downward rather than upward

The sequencer is clocked by an 11-bit timer. Given the timer value t = HHHLLLLLLLL formed by timer high and timer low, this timer is updated every APU cycle (i.e., every second CPU cycle), and counts t, t-1, ..., 0, t, t-1, ..., clocking the waveform generator when it reaches 0. Since the period of the timer is t+1 APU cycles and the sequencer has 8 steps, the period of the waveform is 8*(t+1) APU cycles, or equivalently 16*(t+2) CPU cycles.

Hence

  • fpulse = fCPU/(16*(t+1)) (where fCPU is 1.78977267 MHz for NTSC, 1.662607 MHz for PAL, and 1.773448 MHz for Dendy)
  • t = fCPU/(16*fpulse) - 1

The mixer receives the current envelope volume except when

  • The sequencer output is zero, or
  • The sweep unit is silencing the channel, or
  • The length counter is zero

The behavior of the two pulse channels differs only in the effect of the negate mode of their sweep units.