CPU pinout

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Revision as of 17:06, 2 May 2011 by Tepples (talk | contribs) (Unlikely to affect PPU ports because those are decoded outside the CPU)
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Pin out

AD1 - 01 40 - +5V
AD2 - 02 39 - STR
/RST - 03 38 - E44
A00 - 04 37 - E45
A01 - 05 36 - /OE1
A02 - 06 35 - /OE2
A03 - 07 34 - R/W
A04 - 08 33 - NMI
A05 - 09 32 - /IRQ
A06 - 10 31 - M2
A07 - 11 30 - IOE (usually GND)
A08 - 12 29 - CLK
A09 - 13 28 - D0
A10 - 14 27 - D1
A11 - 15 26 - D2
A12 - 16 25 - D3
A13 - 17 24 - D4
A14 - 18 23 - D5
A15 - 19 22 - D6
GND - 20 21 - D7


Signal description

Active-Low signals are indicated by a "/".

  • CLK is the 21.47727 MHz clock input. Internally, the real clock is derived by dividing the input clock frequency by 12.
  • AD1 and AD2 are the Audio Out pins.
  • Axx is the address bus and Dx the data bus.
  • STR stands for "strobe" and goes to the controller ports ($4016 output latch bit 0), D0 on the controller port pinout
  • /OE1 and /OE2 also go to the controller ports, and each enable the output of their respective controller, if present.
  • E44 and E45 are respectively the expansion port pins 44 and 45 and latched copies of bits 1 and 2 written to $4016
  • R/W is the read/write signal, which is used to indicate operations of the same names. Low is write.
  • /NMI and /IRQ are the two interrupt pins. See the 6502 manual for more detailed explanation.
  • M2 can be considered as a "signals ready" pin. It is actually a delayed form of CLK. In 6502 documentation it's called φ2
  • IOE (tentative name) (pin 30) is special: normally it is grounded in the NES, Famicom, PC10/VS. NES and other Nintendo Arcade Boards (Popeye and Donkey Kong 3), but if it is pulled high, all of the memory-mapped I/O ports (APU/Serial Controller area at $4000-$4015) are disabled, and the chip acts like a 'normal' 6502, just without decimal mode and with the pinout and clock divider of an RP2A03/RP2A07. (What effect does this have on controller ports at $4016/$4017, and how does it interact with $4018-$401A?)