CPU status flag behavior: Difference between revisions
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Two instructions (PLP and RTI) pull a byte from the stack and set flags, but they ignore bits 5 and 4. | Two instructions (PLP and RTI) pull a byte from the stack and set flags, but they ignore bits 5 and 4. | ||
The only way for an IRQ handler to distinguish /IRQ from BRK is to read the flags from the stack and test bit 4. | |||
The slowness of this is one reason why BRK wasn't used as a syscall mechanism. | |||
Revision as of 17:12, 14 July 2010
The flags register, also called processor status or just P, is one of the six architectural registers on the 6502 family CPU.
There are six bits in P:
7654 3210 || |||| || |||+- C: 1 if last addition or shift resulted in a carry, or if || ||| last subtraction resulted in || ||+-- Z: 1 if last operation resulted in a 0 value || |+--- I: Interrupt priority level || | (0: /IRQ and /NMI get through; 1: only /NMI gets through) || +---- D: 1 to make ADC and SBC use binary-coded decimal arithmetic || (ignored on second-source 6502 like that in the NES) |+-------- V: 1 if last ADC or SBC resulted in signed overflow, or | D6 from last BIT read as 0 +--------- N: Set to bit 7 of the last operation
The B flag
There is no "B flag". Bits 5 and 4 of flags do not exist.
Two signals and two instructions can push flags to the stack. When they do so, they fill the unused bits with the following:
| Instruction | Bits 5 and 4 | Side effects after pushing |
|---|---|---|
| PHP | 11 | None |
| BRK | 11 | I is set to 1 |
| /IRQ | 10 | I is set to 1 |
| /NMI | 10 | I is set to 1 |
Two instructions (PLP and RTI) pull a byte from the stack and set flags, but they ignore bits 5 and 4.
The only way for an IRQ handler to distinguish /IRQ from BRK is to read the flags from the stack and test bit 4. The slowness of this is one reason why BRK wasn't used as a syscall mechanism.
