Cartridge connector

Pinout of 60-pin Famicom consoles and cartridges

This diagram represents a top-down view looking directly into the connector. Pins 01-30 are on the label side of the cartridge, left to right.

           -------
GND     - |01   31| - +5V
PRG A11 - |02   32| - M2
PRG A10 - |03   33| - PRG A12
PRG A9  - |04   34| - PRG A13
PRG A8  - |05   35| - PRG A14
PRG A7  - |06   36| - PRG D7
PRG A6  - |07   37| - PRG D6
PRG A5  - |08   38| - PRG D5
PRG A4  - |09   39| - PRG D4
PRG A3  - |10   40| - PRG D3
PRG A2  - |11   41| - PRG D2
PRG A1  - |12   42| - PRG D1
PRG A0  - |13   43| - PRG D0
PRG R/W - |14   44| - PRG /CE ( /A15 + /M2 )
/IRQ    - |15   45| - Audio from 2A03
GND     - |16   46| - Audio to RF
CHR /RD - |17   47| - CHR /WR
CIRAMA10- |18   48| - CIRAM /CE
CHR A6  - |19   49| - CHR /A13
CHR A5  - |20   50| - CHR A7
CHR A4  - |21   51| - CHR A8
CHR A3  - |22   52| - CHR A9
CHR A2  - |23   53| - CHR A10
CHR A1  - |24   54| - CHR A11
CHR A0  - |25   55| - CHR A12
CHR D0  - |26   56| - CHR A13
CHR D1  - |27   57| - CHR D7
CHR D2  - |28   58| - CHR D6
CHR D3  - |29   59| - CHR D5
+5V     - |30   60| - CHR D4
           -------

• The NES and Famicom connectors have a similar arrangement; the NES' connector is mostly a mirror image of the Famicom's.
• Most cartridge PCBs made by Nintendo are numbered the same way as this diagram.
• Most chips and components appear on the opposite side of the PCB from the label in Famicom cartridges.

Pinout of 72-pin NES consoles and cartridges

This diagram represents a top-down view looking directly into the connector. On a front-loader, pins 01-36 are the top side of the connector. Pins 36-01 are on the label side of the cartridge, left to right.

           -------
      +5V |36   72| GND
 CIC toMB |35   71| CIC CLK
CIC toPak |34   70| CIC RST
   CHR D3 |33   69| CHR D4
   CHR D2 |32   68| CHR D5
   CHR D1 |31   67| CHR D6
   CHR D0 |30   66| CHR D7
   CHR A0 |29   65| CHR A13
   CHR A1 |28   64| CHR A12
   CHR A2 |27   63| CHR A10
   CHR A3 |26   62| CHR A11
   CHR A4 |25   61| CHR A9
   CHR A5 |24   60| CHR A8
   CHR A6 |23   59| CHR A7
CIRAM A10 |22   58| CHR /A13
  CHR /RD |21   57| CIRAM /CE
    EXP 4 |20   56| CHR /WR
    EXP 3 |19   55| EXP 5
    EXP 2 |18   54| EXP 6
    EXP 1 |17   53| EXP 7
    EXP 0 |16   52| EXP 8
     /IRQ |15   51| EXP 9
  PRG R/W |14   50| PRG /CE (/A15 + /M2)
   PRG A0 |13   49| PRG D0
   PRG A1 |12   48| PRG D1
   PRG A2 |11   47| PRG D2
   PRG A3 |10   46| PRG D3
   PRG A4 |09   45| PRG D4
   PRG A5 |08   44| PRG D5
   PRG A6 |07   43| PRG D6
   PRG A7 |06   42| PRG D7
   PRG A8 |05   41| PRG A14                   
   PRG A9 |04   40| PRG A13 
  PRG A10 |03   39| PRG A12
  PRG A11 |02   38| M2
      GND |01   37| SYSTEM CLK
           -------

• The NES and Famicom connectors have a similar arrangement; the NES' connector is mostly a mirror image of the Famicom's.
• CHR A10 and CHR A11 are in reverse order on the NES.
• Most cartridge PCBs made by Nintendo are numbered the same way as this diagram.
• Most chips and components appear on the label side of the PCB in NES cartridges.

Signal Descriptions

Notice : Unless specified, those signals are from the console's viewpoint. So an input is a signal driven by the cartridge to the console, and an output a signal driven by the console to the cartridge connector.

• +5V : 5V Power supply from the main voltage regulator.
• GND : 0V power supply.
• SYSTEM CLK : Main oscillator frequency output. It is only available on 72-pin connectors, and its speed varies between NTSC (21MHz) and PAL (27MHz) machines.
• M2 : Also called PHI2 in official docs. This is the CPU clock output. When this signal is high, this means the PRG bus address and data lines are in a stable state and can be latched by external hardware. On reads, the data must be stable until this signal goes low.
• PRG R/W : The Read/Write signal output from the CPU. This signal is high on during CPU reads and low during CPU writes (switches from one mode to another only when M2 is low).
• PRG A0..A14 : Also called just A0..A14 in official docs, or CPU A0..A14 (to not confuse with address outputs of mappers sharing the same number). This is the CPU address bus. It is stable when M2 is high. Note that A15 exists, but is not directly available on the connector.
• PRG D0..D7 : Also called just D0..D7 in official docs, or CPU D0..D7. This is the CPU bidirectional data bus. It goes high impedance on reads, allowing external memory chips to place their data here.
• PRG /CE : Also called /ROMSEL in official docs, to not confuse with PRG /CE output of mappers. This pin outputs the logical NAND of M2 and PRG A15. It is low when the CPU reads or writes to $8000-$FFFF and when the address is stable, allowing to enable ROM chips directly. Advanced mappers use more logic between this pin and the actual PRG /CE (to avoid bus conflicts, for example). Using this signal is the only way to determine the state of A15, so it's needed for any mappers doing any address decoding.
• /IRQ : Interrupt request input. Pull low to trigger an interrupt to the CPU. Can only be connected to an open collector cartridge output (there is an internal pullup resistor in the NES/Famicom). Can be left floating if interrupts aren't used.
• Audio from 2A03 : Audio output from the 2A03's sound generation hardware, already amplified. Only exists with 60-pins connectors.
• Audio to RF : Usually just tied with audio out, this one goes directly to the sound output of the console. This allows cartridges to mix audio with their own audio sources. Not directly present on 72-pins connectors.
• EXP0..9 : Pins that goes to the expansion port on the bottom of the NES units (not present on Famicoms). Have various uses.
• EXP 0 : Used by CopyNES in its cartridge reprogramming mode.
• EXP 2 : Used by some Famicom to NES converters as audio input, because this pin is just straight ahead of the Audio In pin. The NES has to be modified to mix that with the normal audio.
• EXP 5 : Used by MMC5 cartridges as an open emitter input to the cartridge. Pulling this pin high will force the PRG RAM to be transparent to all reads from it, bypassing any state of the MMC5. Writes aren't disabled in this mode, though. Leave this pin unconnected or tie it to ground will have the PRG RAM working normally (MMC5 carts have their internal pulldown resistor). Only a device that plugs in the expansion port under the NES could make an use of this pin.
• EXP 6 : Used by MMC5 cartridges as a Audio In pin. A device that plugs into the expansion port under the NES could allow those cartridge to use the MMC5 audio on a NES without using a screwdriver.
• CHR /WR : Also called /WE in official docs. This signal is low when the PPU is writing. On its falling edge, the address and data are stable.
• CHR /RD : Also called /RD in official docs. This signal is low when the PPU is reading. On its falling edge, the address is stable, and the data should be stable until its rising edge.
• CHR A0..A13 : Also called PA0..13 in official docs, or PPU A0..13 not to confuse with address outputs of mappers sharing the same numbers. This is the PPU's address bus. Most boards tie PA13 directly to the /CE of CHR ROM or CHR RAM to map it into pattern table space ($0000-$1FFF) without any extra logic.
• CHR D0..D7 : Also called PD0..7 in official documentation, or PPU D0..7. This is the PPU's bidirectional data bus. Goes high impedance when CHR /RD goes low allowing memory devices to place their data here.
• CHR /A13 : The inverted form of CHR A13. Typically used to map nametables and attribute tables to $2000-$3FFF.
• CIRAM /CE : Also called VRAM /CS. This signal is used as an input to enable the internal 2k of VRAM (used for name table and attribute tables typically, but could be made for another use). This signal is usually directly connected with CHR /A13, but carts using their own RAM for name table and attribute tables will have their own logic implemented.
• CIRAM A10 : Also called VRAM A10. This is the 1k bank selection input for internal VRAM. This is used to control how the name tables are banked, in other word, this selects nametable mirroring. Connect to CHR A10 for vertical mirroring or CHR A11 for horizontal mirroring. Connect it to a software operated latch to allow bankswitching of two separate name tables in single-screen mirroring (as in AxROM). Many mappers have software operated mirroring selection: they mux CHR A10 and CHR A11 into this pin, selected by a latch.