INES Mapper 014: Difference between revisions

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(worked out the CHR mapping)
m (cleanup)
Line 13: Line 13:
  7  bit  0
  7  bit  0
  ---------
  ---------
  xxxx xxMx
  .... ..M.
        |
        |
        +- MMC3 mode (1: on, 0: off)
        +- MMC3 mode (1: on, 0: off)


* When M is set, writes to $8000-FFFF operate mostly as normal for [[MMC3]].
* When M is set, writes to $8000-FFFF operate mostly as normal for [[MMC3]].
Line 34: Line 34:
* $E001-FFFF odd - as MMC3
* $E001-FFFF odd - as MMC3


=== Ex Mode Clear ===
=== MMC3 Mode Clear ===


When the Ex Mode bit is clear, PRG banking is controlled by a 2 alternative registers, and CHR banking is controlled by 8 alternative registers. These banking registers are independent of the banking registers used when MMC3 Mode is set.
When the MMC3 Mode bit is clear, PRG banking is controlled by a 2 alternative registers, and CHR banking is controlled by 8 alternative registers. These banking registers are independent of the banking registers used when MMC3 Mode is set.


* PRG bank 0 - 8k at $8000-9FFF
* PRG bank 0 - 8k at $8000-9FFF
Line 59: Line 59:
  7  bit  0
  7  bit  0
  ---------
  ---------
  xxxx xxxM
  .... ...M
         |
         |
         +- [[Mirroring]] (0: vertical; 1: horizontal)
         +- [[Mirroring]] (0: vertical; 1: horizontal)
Line 75: Line 75:
  15      bit      0
  15      bit      0
  -------------------
  -------------------
  xABC Dxxx xxxx xxEF
  .ABC D... .... ..EF
 
  CHR bank register: = (%ABC - 3) | %D | %E
  CHR bank register: = (%ABC - 3) | %D | %E



Revision as of 08:22, 4 October 2012


iNES Mapper 014 is an MMC3 variant mapper used in the pirate port of Samurai Spirits by Rex Game Soft. It is very similar to an MMC3, but contains an alternative mode that when used controls banking and mirroring independently of the normal MMC3 mode.

This mapper is not widely supported by emulators.

Registers

The following notes are based on Nestopia's SOMERITEAM SL-1632 mapper implementation.

MMC3 Mode Control: $A131

7  bit  0
---------
.... ..M.
       |
       +- MMC3 mode (1: on, 0: off)
  • When M is set, writes to $8000-FFFF operate mostly as normal for MMC3.
  • When M is clear, alternative functions appear (see MMC3 Mode Clear below).
  • When M is written, the CHR and PRG banks must be switched either to their MMC3 banks (MMC3 Mode Set), or the alternative banks (MMC3 Mode Clear).

MMC3 Mode Set

Note that when the MMC3 Mode bit is set, this mapper operates mostly like the MMC3, except the $A000-BFFE even register does not control the nametable mirroing (it can only be controlled with the MMC3 mode clear). Additionally, a write to the specific address $A131 will alter the MMC3 Mode bit as above.

  • $8000-9FFE even - as MMC3
  • $8001-9FFF odd - as MMC3
  • $A000-BFFE even - ignored
  • $A001-BFFF odd - as MMC3
  • $C000-DFFE even - as MMC3
  • $C001-DFFF odd - as MMC3
  • $E000-FFFE even - as MMC3
  • $E001-FFFF odd - as MMC3

MMC3 Mode Clear

When the MMC3 Mode bit is clear, PRG banking is controlled by a 2 alternative registers, and CHR banking is controlled by 8 alternative registers. These banking registers are independent of the banking registers used when MMC3 Mode is set.

  • PRG bank 0 - 8k at $8000-9FFF
  • PRG bank 1 - 8k at $A000-BFFF
  • PRG fixed - 16k at $C000-FFFF (fixed to last bank)
  • CHR bank 0 - 1k at $0000-03FF
  • CHR bank 1 - 1k at $0400-07FF
  • CHR bank 2 - 1k at $0800-0BFF
  • CHR bank 3 - 1k at $0C00-0FFF
  • CHR bank 4 - 1k at $1000-13FF
  • CHR bank 5 - 1k at $1400-17FF
  • CHR bank 6 - 1k at $1800-1BFF
  • CHR bank 7 - 1k at $1C00-1FFF

$8000-8FFC (0 of 4)

  • Selects 8k PRG bank at $8000-9FFF
  • Only responds if address % $3 is 0

$9000-9FFC (0 of 4)

7  bit  0
---------
.... ...M
        |
        +- Mirroring (0: vertical; 1: horizontal)
  • Selects nametable mirroring. Note that mirroring cannot be set when this mapper is in MMC3 mode.
  • Only responds if address % $3 is 0

$A000-AFFC (0 of 4)

  • Selects 8k PRG bank at $A000-EFFF
  • Only responds if address % $3 is 0

$B000-E003

The address bits select one of 8 CHR bank registers in an unusual way:

15      bit       0
-------------------
.ABC D... .... ..EF

CHR bank register: = (%ABC - 3) | %D | %E

The write to $B000-E003 sets only 4 bits of the CHR bank, selected by the least significant bit of the address (F).

if (!F)
    register = (register & $F0) | (data & $0F)
else
    register = (register & $0F) | ((data << 4) & $F0)