INES Mapper 037: Difference between revisions

From NESdev Wiki
Jump to navigationJump to search
(Traced board, got extended register function from Kinopio, said hi to Karnaugh and DeMorgan.)
 
m (→‎Registers: Replaced with better information from Kinopio)
Line 14: Line 14:
This game, like [[iNES Mapper 047|Super Spike V'Ball + Nintendo World Cup]], replaces PRG RAM with a single register to enforce multiple "jail cells" containing each game.
This game, like [[iNES Mapper 047|Super Spike V'Ball + Nintendo World Cup]], replaces PRG RAM with a single register to enforce multiple "jail cells" containing each game.


The Outer Bank Select register appears to be cleared by the [[CIC lockout chip|CIC]] reset line, so it's not clear what will happen if this game is used in a console without a lockout chip.
The Outer Bank Select register is not cleared on reset, so the reset button is not necessarily sufficient to allow the user to choose a different game.
=== Outer Bank Select ($6000-$7FFF) ===
=== Outer Bank Select ($6000-$7FFF) ===
  7  bit  0
  7  bit  0

Revision as of 04:40, 25 July 2012

iNES Mapper 037 represents the Nintendo of Europe multicart "Super Mario Bros. + Tetris + Nintendo World Cup". It glues together 3 MMC3-compatible games in a single pak.

Overview

  • PRG ROM size: 256 KiB
  • PRG ROM bank size: 8 KiB inner / 64 or 128 KiB outer
  • PRG RAM: Impossible
  • CHR capacity: 256 KiB ROM
  • CHR bank size: 1 and 2 KiB inner / 128 KiB outer
  • Nametable mirroring: Controlled by mapper.
  • Subject to bus conflicts: No

Registers

This game, like Super Spike V'Ball + Nintendo World Cup, replaces PRG RAM with a single register to enforce multiple "jail cells" containing each game.

The Outer Bank Select register is not cleared on reset, so the reset button is not necessarily sufficient to allow the user to choose a different game.

Outer Bank Select ($6000-$7FFF)

7  bit  0
xxxx xQBB
      │││
      │└┴── if 3, forces PRG A16 high regardless of Q bit
      └──── A17 to both PRG and CHR ROM. Additionally, the MMC3's PRG A16 
             is ANDed with this bit before going to PRG ROM (but see above!)

In case that wasn't clear:

Value written PRG window 128kB CHR window
0,1,2 $00000-$0FFFF (64kB) $00000-$1FFFF
3 $10000-$1FFFF (64kB) $00000-$1FFFF
4,5,6 $20000-$3FFFF (128kB) $20000-$3FFFF
7 $30000-$3FFFF (64kB) $20000-$3FFFF

All other registers ($8000-$FFFF)

See MMC3.

Hardware

Since this pak was only ever released with epoxy covering wirebonded silicon dice, the following is guesswork:

It is likely that the support hardware is a 74HC161 and a 74HC00, based on the specific order that the traces enter the epoxy blob. The NAND gates are arranged to calculate

(PRG ROM A16 in) = Q0·Q1 + Q2·(MMC3 PRG A16 out) = Q̿0̿·̿Q̿1̿ ̅·̅ ̅Q̿2̿·̿M̿1̿6̿
(PRG ROM A17 in) = (CHR ROM A17 in) = Q2