INES Mapper 068: Difference between revisions

From NESdev Wiki
Jump to navigationJump to search
(→‎$F000-$FFFF: PRG bank at $8000: update per http://forums.nesdev.com/viewtopic.php?p=106818#p106818)
(→‎Registers: Clarifications. No new info added.)
 
(19 intermediate revisions by 4 users not shown)
Line 1: Line 1:
[[category:iNES Mappers|068]][[Category:in NesCartDB|068]]
{{DEFAULTSORT:068}}[[category:iNES Mappers]][[Category:in NesCartDB]][[Category:Mappers with ROM nametables]][[Category:NES 2.0 mappers with submappers]]


[[iNES Mapper 068]] denotes PCBs using the Sunsoft-4 mapper IC. In the US it was only used in the game ''After Burner''.
[[iNES Mapper 068]] denotes PCBs using the [[Sunsoft 4 pinout|Sunsoft-4 mapper IC]]. In the US it was only used in the game ''After Burner''.
It has the unusual ability to map CHR ROM into the part of the PPU's address space used for nametables.
It has the unusual ability to map CHR ROM into the part of the PPU's address space used for nametables.
Example games:
* ''After Burner''
* ''Maharaja (J)''
* ''Nantettatte!! Baseball (J)''
== Overview ==
* PRG ROM size: Up to 256 KiB
* PRG ROM bank size: 16 KiB
* PRG RAM: Up to 8 KiB
* CHR capacity: Up to 256 KiB ROM
* CHR bank size: 2 KiB
* Nametable [[mirroring]]: Controlled by mapper
* Subject to [[bus conflict]]s: No
== Banks ==
* CPU $6000-$7FFF: 8 KiB PRG RAM bank
* CPU $8000-$BFFF: 16 KiB switchable PRG ROM bank
* CPU $C000-$FFFF: 16 KiB PRG ROM bank, fixed to the last internal bank
* PPU $0000-$07FF: 2 KiB switchable CHR bank
* PPU $0800-$0FFF: 2 KiB switchable CHR bank
* PPU $1000-$17FF: 2 KiB switchable CHR bank
* PPU $1800-$1FFF: 2 KiB switchable CHR bank
* PPU $2000-$23FF (and $2400 or $2800): 1 KiB switchable CHR bank
* PPU $2C00-$2FFF (and $2800 or $2400): 1 KiB switchable CHR bank


== Registers ==
== Registers ==


=== $8000-$8FFF: CHR bank at $0000 ===
=== $6000-$7FFF: Licensing IC ===
Map a 2 KiB CHR ROM bank into PPU $0000.
Only for the game <u>Nantettatte!! Baseball</u>, when WRAM is disabled ($F000.4 is 0), writes to this register reset a timer in the external option ROM cartridge. The external ROM is only readable while banked into $8000-$BFFF and the timer has not expired; once it has, reads from the external ROM should return open bus.
=== $9000-$9FFF: CHR bank at $0800 ===
 
Map a 2 KiB CHR ROM bank into PPU $0800.
The game verifies that the timer expires after 107516 to 107575 M2 cycles (most likely exactly 107520=1024·105) by reading a signature from the end of the external ROM.
=== $A000-$AFFF: CHR bank at $1000 ===
 
Map a 2 KiB CHR ROM bank into PPU $1000.
While WRAM is disabled, reads from $6000-$7FFF return open bus for ''all'' games. (The licensing IC isn't readable because it is connected to only M2, WRAM +CE, WRAM /CE, and R/W. None of the data pins connect.)
=== $B000-$BFFF: CHR bank at $1800 ===
 
Map a 2 KiB CHR ROM bank into PPU $1800.
=== $8000-$8FFF: CHR Pattern Table ROM bank 0 ===
=== $C000-$CFFF: Nametable register 0 ===
Map a 2 KiB CHR ROM bank at PPU address $0000-$07FF.
Map a 1 KiB CHR ROM bank in place of the lower nametable (CIRAM $000-$3FF).
=== $9000-$9FFF: CHR Pattern Table ROM bank 1 ===
Only D6-D0 are used; D7 is ignored and treated as 1, so nametables must be in the last 128 KiB of CHR ROM.
Map a 2 KiB CHR ROM bank at PPU address $0800-$0FFF.
=== $D000-$DFFF: Nametable register 1 ===
=== $A000-$AFFF: CHR Pattern Table ROM bank 2 ===
Map a 1 KiB CHR ROM bank in place of the upper nametable (CIRAM $400-$7FF).
Map a 2 KiB CHR ROM bank at PPU address $1000-$17FF.
Only D6-D0 are used; D7 is ignored and treated as 1.
=== $B000-$BFFF: CHR Pattern Table ROM bank 3 ===
Map a 2 KiB CHR ROM bank at PPU address $1800-$1FFF.
=== $C000-$CFFF: CHR Nametable ROM bank 0 ===
Map a 1 KiB CHR ROM bank where CIRAM $000-$3FF would normally be mapped.
* This applies only when $E000.4 = 1 for ROM nametable mode.
* This occupies the lower nametable and pattern table.
* The PPU address range of this bank follows the mirroring selection in $E000.
* Only D6-D0 are used; D7 is ignored and treated as 1, so nametables must be in the last 128 KiB of CHR ROM.
=== $D000-$DFFF: CHR Nametable ROM bank 1 ===
Map a 1 KiB CHR ROM bank where CIRAM $400-$7FF would normally be mapped.
* This applies only when $E000.4 = 1 for ROM nametable mode.
* This occupies the upper nametable and pattern table.
* The PPU address range of this bank follows the mirroring selection in $E000.
* Only D6-D0 are used; D7 is ignored and treated as 1.
=== $E000-$EFFF: Nametable control ===
=== $E000-$EFFF: Nametable control ===
<pre>
<pre>
7654 3210
7654 3210
   |   |
   |   ||
   |   +- Mirroring
   |   ++- Nametable Mirroring Behavior (See table below.)
  |      0: vertical (0101); 1: horizontal (0011);
   +------ CIRAM / CHR-ROM Select for Nametables (PPU $2000-$2FFF):
   |      2: 1-screen (0000); 3: 1-screen (1111)
            0 = CIRAM
  +------ Chip select for PPU $2000-$2FFF (nametables):
            1 = CHR-ROM (Uses ROM bank selection registers $C000, $D000.)
          0 for CIRAM or 1 for CHR ROM
</pre>
</pre>
Nametable [[mirroring]] works the same way in both CIRAM and CHR ROM modes.
Not all documents mention the single screen mirroring mode; its behavior should be verified against an authentic cartridge.


=== $F000-$FFFF: PRG bank at $8000 ===
==== Nametable Mirroring Behavior ====
7  bit  0
{| class="wikitable"
---- ----
! Mode !! $E000.(1:0) !! PPU $2000-$23FF !! PPU $2400-$27FF !! PPU $2800-$2BFF !! PPU $2C00-$2FFF
...E BBBB
|-
  | ||||
| Vertical || %00 || Low NT || High NT || Low NT || High NT
  | ++++- Select 16 KiB PRG banked into $8000-$BFFF
|-
  +------ Enable PRG RAM +CS2
| Horizontal || %01 || Low NT || Low NT || High NT || High NT
|-
| Single-screen NT0 || %10 || Low NT || Low NT || Low NT || Low NT
|-
| Single-screen NT1 || %11 || High NT || High NT || High NT || High NT
|-
|}
 
Note: Nametable [[mirroring]] works the same way in both CIRAM and CHR-ROM modes.
 
=== $F000-$FFFF: PRG-ROM bank ===
Map a 16 KiB PRG ROM bank at CPU address $8000-$BFFF.
 
7  bit  0
---- ----
...E BBBB
    | ||||
    | ++++- Select 16 KiB PRG banked into $8000-$BFFF
    +------ 1:Enable PRG RAM = WRAM +CS2
 
<u>Nantettatte!! Baseball</u> repurposes some of the bits:
7  bit  0
---- ----
...E RBBB
    | ||||
    | |+++- Select 16 KiB PRG banked into $8000-$BFFF
    | +----  1: select internal ROM
    |        0: select external ROM
    +------ 1: Enable PRG RAM = WRAM +CS2
            0: Enable licensing verification
 
Note that although the external ROM could be up to 128KiB, both known subcartridges contain 16KiB of data, doubled to fill a 32KiB EPROM, mirrored across the bottom 128KiB.
 
The fixed bank is always from the internal ROM.


== Hardware ==
== Hardware ==
Both the US and Japanese release of ''After Burner'' have CHR ROM split into two chips.
The US release of ''After Burner'' has CHR ROM split into [http://bootgod.dyndns.org:7777/profile.php?id=326 two 28-pin chips].
The Japanese releases exist both as [http://bootgod.dyndns.org:7777/profile.php?id=3806 two 32-pin 128KiB CHR ROMs with extra enables] and as [http://forums.nesdev.org/viewtopic.php?p=106818#p106818 one 32-pin 256KiB ROM].


== References ==
== References ==
*[http://nesdev.org/sunsoft.txt Goroh's Sunsoft mapper doc]
*[http://nesdev.org/sunsoft.txt Goroh's Sunsoft mapper doc]
 
*[http://forums.nesdev.org/viewtopic.php?t=9744 Naruko's notes in the forum]
  Here are Disch's original notes:
*[http://www.romhacking.net/documents/362/ NES Mapper List] by Disch
  ========================
*[http://nesdev.org/mappers.zip Comprehensive NES Mapper Document] by \Firebug\, information about mapper's initial state is inaccurate.
  =  Mapper 068          =
  ========================
 
 
  Example Games:
  --------------------------
  After Burner 2
  Maharaja
 
 
  Registers:
  ---------------------------
 
  Range,Mask:  $8000-FFFF, $F000
 
    $8000:  CHR Reg 0  (2k @ $0000)
    $9000:  CHR Reg 1  (2k @ $0800)
    $A000:  CHR Reg 2  (2k @ $1000)
    $B000:  CHR Reg 3  (2k @ $1800)
 
    $C000:  [.NNN NNNN]  NT-ROM Reg 0
    $D000: [.NNN NNNN]  NT-ROM Reg 1
    $E000:  [...R ...M]  Mirroring (see section below)
 
    $F000:  PRG Reg (16k @ $8000)
 
 
  CHR Setup:
  ---------------------------
 
        $0000  $0400  $0800  $0C00  $1000  $1400  $1800  $1C00
      +---------------+---------------+---------------+---------------+
      |    $8000    |    $9000    |    $A000    |    $B000    |
      +---------------+---------------+---------------+---------------+
 
 
  PRG Setup:
  ---------------------------
 
        $8000  $A000  $C000  $E000 
      +---------------+---------------+
      |    $F000    |    { -1}    |
      +---------------+---------------+
 
 
 
  Mirroring:
  ---------------------------
 
  The mirroring reg has two significant bits:
 
    $E000:  [...R ...M]
 
    'M' selects H/V:
      0 = Vert
      1 = Horz
 
    'R' selects whether or not to use CHR-ROM as nametables.
      0 = normal mirroring
      1 = use CHR-ROM
 
  When 'R' is set, $C000 and $D000 are used to select 1k CHR-ROM pages to use as nametables.  They are arranged
  in either Horz or Vert mirroring fashion depending on the 'M' bit ($C000 would be used in place of NTA,
  $D000 in place of NTB).
 
  R=1, M=0:
        [ $C000 ][ $D000 ]
        [ $C000 ][ $D000 ]
 
  R=1, M=1:
        [ $C000 ][ $C000 ]
        [ $D000 ][ $D000 ]
 
  Note that CHR-ROM for nametables is taken from the last 128k of CHR.  This means you must effectively OR the
  value written to $C000/$D000 with $80.

Latest revision as of 16:57, 7 December 2021


iNES Mapper 068 denotes PCBs using the Sunsoft-4 mapper IC. In the US it was only used in the game After Burner. It has the unusual ability to map CHR ROM into the part of the PPU's address space used for nametables.

Example games:

  • After Burner
  • Maharaja (J)
  • Nantettatte!! Baseball (J)

Overview

  • PRG ROM size: Up to 256 KiB
  • PRG ROM bank size: 16 KiB
  • PRG RAM: Up to 8 KiB
  • CHR capacity: Up to 256 KiB ROM
  • CHR bank size: 2 KiB
  • Nametable mirroring: Controlled by mapper
  • Subject to bus conflicts: No

Banks

  • CPU $6000-$7FFF: 8 KiB PRG RAM bank
  • CPU $8000-$BFFF: 16 KiB switchable PRG ROM bank
  • CPU $C000-$FFFF: 16 KiB PRG ROM bank, fixed to the last internal bank
  • PPU $0000-$07FF: 2 KiB switchable CHR bank
  • PPU $0800-$0FFF: 2 KiB switchable CHR bank
  • PPU $1000-$17FF: 2 KiB switchable CHR bank
  • PPU $1800-$1FFF: 2 KiB switchable CHR bank
  • PPU $2000-$23FF (and $2400 or $2800): 1 KiB switchable CHR bank
  • PPU $2C00-$2FFF (and $2800 or $2400): 1 KiB switchable CHR bank

Registers

$6000-$7FFF: Licensing IC

Only for the game Nantettatte!! Baseball, when WRAM is disabled ($F000.4 is 0), writes to this register reset a timer in the external option ROM cartridge. The external ROM is only readable while banked into $8000-$BFFF and the timer has not expired; once it has, reads from the external ROM should return open bus.

The game verifies that the timer expires after 107516 to 107575 M2 cycles (most likely exactly 107520=1024·105) by reading a signature from the end of the external ROM.

While WRAM is disabled, reads from $6000-$7FFF return open bus for all games. (The licensing IC isn't readable because it is connected to only M2, WRAM +CE, WRAM /CE, and R/W. None of the data pins connect.)

$8000-$8FFF: CHR Pattern Table ROM bank 0

Map a 2 KiB CHR ROM bank at PPU address $0000-$07FF.

$9000-$9FFF: CHR Pattern Table ROM bank 1

Map a 2 KiB CHR ROM bank at PPU address $0800-$0FFF.

$A000-$AFFF: CHR Pattern Table ROM bank 2

Map a 2 KiB CHR ROM bank at PPU address $1000-$17FF.

$B000-$BFFF: CHR Pattern Table ROM bank 3

Map a 2 KiB CHR ROM bank at PPU address $1800-$1FFF.

$C000-$CFFF: CHR Nametable ROM bank 0

Map a 1 KiB CHR ROM bank where CIRAM $000-$3FF would normally be mapped.

  • This applies only when $E000.4 = 1 for ROM nametable mode.
  • This occupies the lower nametable and pattern table.
  • The PPU address range of this bank follows the mirroring selection in $E000.
  • Only D6-D0 are used; D7 is ignored and treated as 1, so nametables must be in the last 128 KiB of CHR ROM.

$D000-$DFFF: CHR Nametable ROM bank 1

Map a 1 KiB CHR ROM bank where CIRAM $400-$7FF would normally be mapped.

  • This applies only when $E000.4 = 1 for ROM nametable mode.
  • This occupies the upper nametable and pattern table.
  • The PPU address range of this bank follows the mirroring selection in $E000.
  • Only D6-D0 are used; D7 is ignored and treated as 1.

$E000-$EFFF: Nametable control

7654 3210
   |   ||
   |   ++- Nametable Mirroring Behavior (See table below.)
   +------ CIRAM / CHR-ROM Select for Nametables (PPU $2000-$2FFF):
             0 = CIRAM
             1 = CHR-ROM (Uses ROM bank selection registers $C000, $D000.)

Nametable Mirroring Behavior

Mode $E000.(1:0) PPU $2000-$23FF PPU $2400-$27FF PPU $2800-$2BFF PPU $2C00-$2FFF
Vertical %00 Low NT High NT Low NT High NT
Horizontal %01 Low NT Low NT High NT High NT
Single-screen NT0 %10 Low NT Low NT Low NT Low NT
Single-screen NT1 %11 High NT High NT High NT High NT

Note: Nametable mirroring works the same way in both CIRAM and CHR-ROM modes.

$F000-$FFFF: PRG-ROM bank

Map a 16 KiB PRG ROM bank at CPU address $8000-$BFFF.

7  bit  0
---- ----
...E BBBB
   | ||||
   | ++++- Select 16 KiB PRG banked into $8000-$BFFF
   +------ 1:Enable PRG RAM = WRAM +CS2

Nantettatte!! Baseball repurposes some of the bits:

7  bit  0
---- ----
...E RBBB
   | ||||
   | |+++- Select 16 KiB PRG banked into $8000-$BFFF
   | +----   1: select internal ROM
   |         0: select external ROM
   +------ 1: Enable PRG RAM = WRAM +CS2
           0: Enable licensing verification

Note that although the external ROM could be up to 128KiB, both known subcartridges contain 16KiB of data, doubled to fill a 32KiB EPROM, mirrored across the bottom 128KiB.

The fixed bank is always from the internal ROM.

Hardware

The US release of After Burner has CHR ROM split into two 28-pin chips. The Japanese releases exist both as two 32-pin 128KiB CHR ROMs with extra enables and as one 32-pin 256KiB ROM.

References