INES Mapper 176: Difference between revisions

From NESdev Wiki
Jump to navigationJump to search
(Two more notes)
 
(46 intermediate revisions by 2 users not shown)
Line 1: Line 1:
[[Category:iNES Mappers|176]]
{{DEFAULTSORT:176}}[[Category:iNES Mappers]][[Category:Multicart mappers]][[Category:MMC3-like mappers]][[Category:MMC3 with CHR ROM and CHR RAM]][[Category:Mappers with scanline IRQs]][[Category:Mappers with large PRG RAM]][[Category:NES 2.0 mappers with submappers]]
Mapper 176 is used by FK23C- and FK23CA-based multicarts as well as the re-releases of Waixing games that were originally released on boards using a variety of mappers. Being primarily designed for multicarts, it consists of an MMC3 clone with extended PRG and CHR bankswitch registers.  
'''iNES Mapper 176''' denotes the '''8025''' enhanced [[MMC3]] chipset. It used by many multicarts, Chinese single-game and educational computer cartridges, and Techno Source's ''Intellivision X2'' Plug-and-Play console. Incompatible variations exist that are denoted via NES 2.0 Submapper.


PRG and CHR bank switching is done via the normal MMC3 registers, whose high bits can be masked off if necessary, before being ORed with higher-order PRG and CHR Base bank bits. Additional Mode bits can be set to disable MMC3 PRG and/or CHR banking to solely use the PRG and CHR base directly as bank numbers in a GNROM-like fashion. A special CNROM mode allows ORing the CHR base with a data latch that responds to writes in the $8000-$FFFF range (except $A000-$BFFF). A few multicart menus use an extended MMC3 mode that provides full 1 KiB CHR bank granularity and switching the PRG banks that in a normal MMC3 are fixed. The RAM Configuration Register enables 32 KiB of WRAM, 16 KiB of which are non-volatile, and allows specifying that only the first 8 KiB of CHR memory are RAM.
{| class="wikitable"
! colspan="13" | Submappers
|-
! rowspan="2" | # !! rowspan="2" | PCB codes !! rowspan="2" | [[UNIF]] MAPR !! colspan="5" | MMC3 !! colspan="4" | Outer bank registers !! rowspan="2" | Example
|-
! Ext. mode !! PRG bits !! $46/47 !! [[Mirroring#Single-Screen|1SM]] !! Extra WRAM !! Address mask !! PRG A21+ !! CHR A21+ !! CNROM latch
|-
| 0 || LP-8002KB, SFC-12B || '''BMC-Super24in1SC03'''  || - || 6 || normal || - || - || $Fxx3 || - || - || - || ''YH-xxx'' multicarts, ''Rockman 6-in-1''
|-
| 1 || FK-xxx/BS-xxx || '''BMC-FK23C'''/'''BMC-FK23CA''' || $5FF3.1 || 8 || normal || - || - || $Fxx3 || - || - || yes || ''FK-xxxx'' multicarts
|-
| 2 || FS005/FS006 || '''WAIXING-FS005''' || $5FF3.1 || 6 || swapped || yes || $A001.0-1 || $Fxx3 || $5xx0.3/7, $5xx2.6-7/5 || - || - || Waixing 2005+ re-releases, ''245-in-1 Real Game''
|-
| 3 || JX9003B || - || - || 8 || normal || - || - || $Fxx7 || $5xx5 || $5xx6 || - || ''Super Mario 160-in-1 Funny Time''
|-
| 4 || ? || - || - || 6 || normal || - || - || $Fxx3 || $5xx2.7 || - || - || ''GameStar Smart Genius Deluxe''
|-
| 5 || HST-162|| - || - || 6 || normal || - || - || $Fxx3 || $4800 || - || - || ''Game 500-in-1''
|-
|}
* The '''SFC-12B''' PCB (submapper 0) mounts both CHR-ROM and CHR-RAM that are selected via $5xx0.5.
* Eight MMC3 PRG bits mean that bit 6 and 7 of $8000.6/7 are applied, and the fixed banks are $FE/$FF rather than $3E/$3F. This implies that the multicart's reset vector lies at address PRG-ROM address $1FFFFC rather than $7FFFC if the PRG-ROM is that large.
=Registers=
'''FS005 (Submapper 2)''' can disable the registers in the $5000-$5FFF range using the [[#RAM Configuration Register ($A001)|RAM Configuration Register ($A001)]]. The same register also enables a mixed CHR-ROM/CHR-RAM mode that is similar to [[INES Mapper 195]].


Except for [https://wiki.nesdev.org/w/index.php?title=INES_Mapper_176#1:_Extra_PRG_for_multicart_menu Variant 1], the power-on state is that all new registers are initialized to $00, causing the FK23C to mimic a standard MMC3, which means that the 8 KiB bank in CPU space at $E000 is the bank that ends the first 512 KiB ($7E000), even if the ROM image is larger than that.
==Mode Register ($5xx0)==
 
Mask: $F''xx''7 ('''Submapper 3'''), $5''xx''3 (all others), ''x'' determined by [[#Solder Pad|solder pad setting]]
==Registers==
FK23CA-variant boards have a DIP switch that changes the address mask at which the board hardware responds to CPU writes in the $5000-$5FFF range. The address mask is $10 SHL DIP, e.g. a DIP value of zero results in an address mask of $5010, a value of one in an address mask of $5020, and so on. Multicarts determine the DIP setting by attempting a PRG bankswitch at $5011, $5021, $5041, then checking after each attempt whether the bankswitch actually occured; subsequently registers are accessed at $5FFx, which will trigger a write at any DIP switch setting. A DIP setting of zero (address mask $5010) will produce a usable result for any ROM image, although the multicart's menu is sometimes found at other settings; such ROMs will not be recognizable as multicarts on emulators that do not allow changing the DIP switch setting and will instead appear to be oversized variants of one of the individual games.
 
Note that the registers in the $5000-$5FFF range can be temporarily disabled by the RAM Configuration Register ($A001). Waixing games do this apparently for protection purposes.
 
===Mode Register ($5xx0)===
  7654 3210
  7654 3210
  ---- ----
  ---- ----
  PCTm PMMM
  PCTm PMMM
  |||| ||||
  |||| ||||
  |||| |+++- PRG Mode/Mask (*1)
  |||| |+++- Select PRG Banking Mode (ignored in Extended MMC3 Mode)
  |||| |      0: MMC3 Bank AND $3F OR ((PRG Base SHL 1) AND NOT $3F)
  |||| |      0: MMC3 PRG Mode, 2 MiB/512 KiB Outer PRG Bank Size
  |||| |      1: MMC3 Bank AND $1F OR ((PRG Base SHL 1) AND NOT $1F)
  |||| |      1: MMC3 PRG Mode, 256 KiB Outer PRG Bank Size
  |||| |      2: MMC3 Bank AND $0F OR ((PRG Base SHL 1) AND NOT $0F)
  |||| |      2: MMC3 PRG Mode, 128 KiB Outer PRG Bank Size
  |||| |      3: PRG Base selects the same 16 KiB PRG bank at CPU $8000 and $C000
  |||| |      3: NROM-128 PRG Mode, 16 KiB PRG at $8000-$BFFF mirrored at $C000-$FFFF
  |||| |      4: PRG Base SHR 1 selects 32 KiB PRG bank at CPU $8000
  |||| |      4: NROM-256 PRG Mode, 32 KiB PRG at $8000-$FFFF
  |||| |      5-7: Never used
  |||| |      5: UNROM PRG Mode, 16 KiB PRG at $8000-$BFFF, inner bank #7 at $C000-$FFFF
  |||| +---- PRG Base bit 7
|||| |      6-7: Never used
  |||+------ CHR Mask
  |||| +---- PRG A21 ('''Submapper 2''' only)
  |||        0: $FF in MMC3 CHR Mode (bit 6 clear), $03 in CNROM Mode ($5xx0 bit 6 set and $5xx3 bit 2/6 set)
  |||+------ Select Outer CHR Bank Size
  |||        1: $FF/$FF/$7F (selected by bits 0-2) in MMC3 CHR Mode (bit 6 clear), $01 in CNROM Mode ($5xx0 bit 6 set and $5xx3 bit 2/6 set)
  |||        0: In MMC3 CHR Mode: 256 KiB
  ||+------- CHR Type (0: ROM, 1: RAM) (*2)
|||            In CNROM CHR Mode: 32 KiB ('''Submapper 1''' only)
  |+-------- CHR Mode
  |||        1: In MMC3 CHR Mode: 128 KiB
  |          0: MMC3 Bank AND CHR Mask (bit 4)
|||            In CNROM CHR Mode: 16 KiB ('''Submapper 1''' only)
  |          1: CHR Base selects 8 KiB CHR bank at PPU $8000. If CNROM Mode is active, the CNROM latch ANDed with the mask set by bit 4 and ORed with the CHR base.
  ||+------- '''Submappers 0/1''' with both CHR-ROM and CHR-RAM (e.g. '''SFC-12B''' PCB):
  +--------- PRG Base bit 8
||          0: Select CHR-ROM
||          1: Select CHR-RAM
||        '''Submapper 1''' with $5xx0.6=1:
||          0: Enable CNROM latch (CNROM mode)
||          1: Disable CNROM latch (NROM mode)
  |+-------- CHR A10-12 Mode
  |          0: from MMC3
  |          1: from PPU
  +--------- PRG A22 ('''Submapper 2''' only)
Power-on value: $00


* (*1) In Extended MMC3 Mode ($5xx3 bit 1 set), the MMC3 Bank mask is $7F regardless of the value of $5xx0 bits 0 to 2.
==PRG Base Register LSB ($5xx1)==
* (*2) The CHR Type (bit 5) is only meaningful on carts that have both CHR-RAM and CHR-ROM, such as the Rockman I-VI multicart. On carts that only have one type of CHR memory, this bit cannot be relied upon to correctly specify the installed memory type.
Mask: $F''xx''7 ('''Submapper 3'''), $F''xx''3 (all others), ''x'' determined by [[#Solder Pad|solder pad setting]]
 
===PRG Base Register ($5xx1)===
  7654 3210
  7654 3210
  ---- ----
  ---- ----
  .PPP PPPP
  .PPP PPPP
   ||| ||||
   ||| ||||
   +++-++++- PRG Base bits 0-6
   +++-++++- PRG A20..A14
Power-on value: $00
Depending on the PRG banking mode set via $5xx0, only the higher bits of this register are applied:
PRG A..
21111111
09876543
--------
MMMMMMMM  Submappers 1/3 in PRG Mode 0 (MMC3 2 MiB) or Extended MMC3 Mode
BBMMMMMM  Submappers 0/2/4 in PRG Mode 0 (MMC3 512 KiB)
BBBMMMMM  PRG Mode 1 (MMC3 256 KiB)
BBBBMMMM  PRG Mode 2 (MMC3 128 KiB)
BBBBBBBC  PRG Mode 3 (NROM-128)
BBBBBBCC  PRG Mode 4 (NROM-256)
BBBBLLLC  PRG Mode 5 (UNROM)
M: Bit comes from MMC3 ($8000.6/7 or fixed bank)
B: Bit comes from PRG Base Register ($5xx1)
L: Bit comes from UNROM Latch ($8000-$FFFF or fixed bank)
C: Bit comes from CPU
 
'''Submapper 5''' only selects PRG A14-A18 (i.e. 512 KiB) via this register, selecting upper PRG bits via register [[#PRG Base Register MSB ($4800), Submapper 5 only|$4800]].
==PRG Base Register MSB ($5xx5), Submapper 3 only==
Mask: $F''xx''7 ('''Submapper 3'''), ''x'' determined by [[#Solder Pad|solder pad setting]]
7654 3210
---- ----
.... PPPP
      ||||
      ++++- PRG Base A24..A21
Power-on value: $00
==PRG Base Register MSB ($4800), Submapper 5 only==
Mask: $F800
7654 3210
---- ----
..PP PPPP
  || ||||
  ++-++++- PRG Base A24..A19
Power-on value: $00


===CHR Base Register ($5xx2)===
==CHR Base Register LSB ($5xx2)==
Mask: $F''xx''7 ('''Submapper 3'''), $5''xx''3 (all others), ''x'' determined by [[#Solder Pad|solder pad setting]]
  7654 3210
  7654 3210
  ---- ----
  ---- ----
  CPCC CCCC
  ccdC CCCC
  |||| ||||
  |||| ||||
  ++++-++++- CHR Base bits 0-7
  ++++-++++- CHR A20..A13
  |
||+------- PRG A25 ('''Submapper 2''' only)
  +-------- also: PRG Base bit 9
++-------- PRG A24..A23 ('''Submapper 2''' only)
+--------- PRG A21 ('''Submapper 4''')
Power-on value: $00
 
Depending on the CHR banking mode set via $5xx0, only the higher bits of this register are applied:
CHR A..
21111111111
09876543210
-----------
BBBMMMMMMMM  MMC3 CHR Mode ($5xx0.6=0), 256 KiB ($5xx0.4=0)
BBBBMMMMMMM  MMC3 CHR Mode ($5xx0.6=0), 128 KiB ($5xx0.4=1)
BBBBBBLLPPP  CNROM CHR Mode ($5xx0.6=1, $5xx0.5=0), 32 KiB ($5xx0.4=0), '''Submapper 1''' only
BBBBBBBLPPP  CNROM CHR Mode ($5xx0.6=1, $5xx0.5=0), 16 KiB ($5xx0.4=1), '''Submapper 1''' only
BBBBBBBBPPP  NROM CHR Mode ($5xx0.6=1, $5xx0.5=1 or '''Submapper''' other than '''1''')
M: Bit comes from MMC3 ($8000.0-5)
B: Bit comes from CHR Base Register ($5xx2)
L: Bit comes from CNROM Latch ($8000-$FFFF)
P: Bit comes from PPU
 
==CHR Base Register MSB ($5xx6), Submapper 3 only==
Mask: $F''xx''7 ('''Submapper 3'''), ''x'' determined by [[#Solder Pad|solder pad setting]]
 
7654 3210
---- ----
.... PPPP
      ||||
      ++++- CHR Base A24..A21
Power-on value: $00
 
==Extended Mode Register ($5xx3), Submappers 1-2 only==
Mask: $F''xx''3, ''x'' determined by [[#Solder Pad|solder pad setting]]


Writing to the CHR Base Register also resets the CNROM latch.
===Extended Mode Register ($5xx3)===
  7654 3210
  7654 3210
  ---- ----
  ---- ----
  .C.. .CE.
  .?.. .?E.
  |    ||  
        |  
  |    |+- Extended MMC3 Mode (0: disable, 1: enable)
        +- [[#MMC3-compatible registers ($8000/$8001, $A000, $C000/$C001, $E000/$E001)|Extended MMC3 Mode]]
  +----+-- CNROM mode (0: disable, 1: enable)
            0: disable
            1: enable
Power-on value: $00
Most multicarts write value $44 rather than $00 to disable Extended MMC3 Mode. Hardware tests do not indicate any difference in behavior between writing $00 and $44.
==Mirroring Register ($A000)==
Mask: $E003
7654 3210
---- ----
.... ..MM
        ++- Select nametable mirroring
            0: Vertical
            1: Horizontal
            2: Single-screen, page 0 ('''Submapper 2''' only)
            3: Single-screen, page 1 ('''Submapper 2''' only)
Power-on value: $00


Since all games that use CNROM mode always set both bits 2 and 6 simultaneously, it's not clear which one of these bits actually triggers the CNROM mode, and what the function of the other bit would be.
Single-screen mirroring is only available when the RAM Configuration Register is enabled ($A001.5).
 
==RAM Configuration Register ($A001), Submapper 2 only==
Mask: $E003


===RAM Configuration Register ($A001)===
This register functions like MMC3 register $A001 until bit 5 is set, which turns it into the RAM Configuration Register.
This register functions like MMC3 register $A001 until bit 5 is set, which turns it into the RAM Configuration Register.


  7654 3210
  7654 3210
  ---- ----
  ---- ----
  RFE. ?CWW
  RFE. SCWW
  |||  ||||
  |||  ||||
  |||  ||++- Select 8 KiB PRG-RAM bank at $6000-$7FFF. Ignored if Bit 5 is clear.
  |||  ||++- Select 8 KiB PRG-RAM bank at $6000-$7FFF. Ignored if Bit 5 is clear.
  |||  |+--- First 8 KiB of CHR space. Ignored if Bit 5 is clear.
  |||  |+--- Select the memory type in the first 8 KiB of CHR space. Ignored if Bit 5 is clear.
  |||  |      0: First 8 KiB are CHR-ROM
  |||  |      0: First 8 KiB are CHR-ROM
  |||  |      1: First 8 KiB are CHR-RAM
  |||  |      1: First 8 KiB are CHR-RAM
  |||  +---- Set to 1 by some Waixing games, meaning unknown
  |||  +---- Unknown
  ||+------- RAM Configuration Register Enable
  ||+------- RAM Configuration Register Enable
  ||          0: RAM Configuration Register disabled, $A001 functions like on MMC3, 8 KiB of WRAM
  ||          0: RAM Configuration Register disabled, $A001 functions as on MMC3, 8 KiB of WRAM
  ||          1: RAM Configuration Register enabled, 32 KiB of WRAM
  ||          1: RAM Configuration Register enabled, 32 KiB of WRAM
  |+-------- FK23C Registers Enable. Ignored if Bit 5 is clear.
  |+-------- Outer Bank Registers Enable. Ignored if Bit 5 is clear.
  |          0: FK23C Registers disabled, $5000-$5FFF maps to the second 4 KiB of the 8 KiB WRAM bank 2
  |          0: Outer Bank Registers disabled, $5000-$5FFF maps to the second 4 KiB of the 8 KiB WRAM bank 2
  |          1: FK23C Registers enabled in the $5000-$5FFF range
  |          1: Outer Bank Registers enabled in the $5000-$5FFF range
  +--------- PRG RAM enable (0: disable, 1: enable)
  +--------- PRG RAM enable (0: disable, 1: enable)
Power-on value: $00
==UNROM latch ($8000-$FFFF)==
In UNROM Mode (PRG Mode 5), writing to this address range changes the 16 KiB inner PRG bank at $8000-$BFFF.
==CNROM latch ($8000-$FFFF), Submapper 1 only==
In CNROM Mode, writing to this address range changes the inner CHR bank.


Of the four 8 KiB WRAM banks, only bank 1 and 3 are non-volatile. Games usually use bank 0 as work RAM, bank 2 for protection, and banks 1 and 3 for save game data. The protection check involves disabling the FK23C registers in the $5000-$5FFF range by writing $Ax to $A001, then writing some code to $5000-$5FFF range which will land in the second half of WRAM bank 2. After re-enabling the FK23C registers and copying save game data from banks 1 and/or 3 into work RAM in bank 0, bank 2 is switched in, and the code originally written via the $5000-$5FFF window is executed, which in many games is just a simple RTS.
==MMC3-compatible registers, Extended MMC3 Mode ($8000/$8001, $C000/$C001, $E000/$E001)==
Mask: $E003 (verified on real hardware)


===CNROM latch ($8000-$9FFF, $C000-$FFFF)===
Some multicart games depend on writes to $9FFF not doing anything as a result of the MMC3 address mask being $E003 rather than the standard $E001.
If CNROM Mode is active ($5xx0 bit 6 set and $5xx3 bit 2/6 set), writes to these ranges will update a data latch similar to a normal [[INES Mapper 003|CNROM]] board, with the latch value being masked according to $5xx0 bit 4 before being ORed with the CHR Base.


===MMC3-compatible registers ($8000/$8001, $A000, $C000/$C001, $E000/$E001)===
If the "Extended MMC3 Mode" bit in register $5xx3 is clear, then these registers function identically to the [[MMC3]]. On '''Submappers 1 and 2''', if the "Extended MMC3 Mode" bit is set, four more bank registers become available at [[MMC3#Bank_select_.28.248000-.249FFE.2C_even.29|$8000/$8001]], so that the original two 2 KiB CHR banks become four 1 KiB CHR banks, and the two fixed 8 KiB PRG banks become selectable, similar to the [[RAMBO-1]].  Register $8000 if $5xx3 bit 1 is set:
If the "Extended MMC3 Mode" bit in register $5xx3 is clear, then these registers function identically to the [[MMC3]]. If the "Extended MMC3 Mode" bit is set, four more bank registers become available at [https://wiki.nesdev.org/w/index.php/MMC3#Bank_select_.28.248000-.249FFE.2C_even.29 $8000/$8001], so that the original two 2 KiB CHR banks become four 1 KiB CHR banks, and the two fixed 8 KiB PRG banks become selectable:
  7  bit  0
  7  bit  0
  ---- ----
  ---- ----
Line 95: Line 216:
  ||  ||||
  ||  ||||
  ||  ++++- Specify which bank register to update on next write to Bank Data register
  ||  ++++- Specify which bank register to update on next write to Bank Data register
  ||        0: Select 1 KB CHR bank at PPU $0000-$03FF (or $1000-$13FF)
  ||        $0: Select 1 KB CHR bank at PPU $0000-$03FF (or $1000-$13FF)
  ||        1: Select 1 KB CHR bank at PPU $0800-$0BFF (or $1800-$1BFF)
  ||        $1: Select 1 KB CHR bank at PPU $0800-$0BFF (or $1800-$1BFF)
  ||        2: Select 1 KB CHR bank at PPU $1000-$13FF (or $0000-$03FF)
  ||        $2: Select 1 KB CHR bank at PPU $1000-$13FF (or $0000-$03FF)
  ||        3: Select 1 KB CHR bank at PPU $1400-$17FF (or $0400-$07FF)
  ||        $3: Select 1 KB CHR bank at PPU $1400-$17FF (or $0400-$07FF)
  ||        4: Select 1 KB CHR bank at PPU $1800-$1BFF (or $0800-$0BFF)
  ||        $4: Select 1 KB CHR bank at PPU $1800-$1BFF (or $0800-$0BFF)
  ||        5: Select 1 KB CHR bank at PPU $1C00-$1FFF (or $0C00-$0FFF)
  ||        $5: Select 1 KB CHR bank at PPU $1C00-$1FFF (or $0C00-$0FFF)
  ||        6: Select 8 KB PRG ROM bank at $8000-$9FFF (or $C000-$DFFF)
  ||        $6: Select 8 KB PRG ROM bank at $8000-$9FFF (or $C000-$DFFF)
  ||        7: Select 8 KB PRG ROM bank at $A000-$BFFF
  ||        $7: Select 8 KB PRG ROM bank at $A000-$BFFF
  ||        8: Select 8 KB PRG ROM bank at $C000-$DFFF (or $8000-$9FFF)
  ||        $8: Select 8 KB PRG ROM bank at $C000-$DFFF (or $8000-$9FFF)
  ||        9: Select 8 KB PRG ROM bank at $E000-$FFFF
  ||        $9: Select 8 KB PRG ROM bank at $E000-$FFFF
  ||        A: Select 1 KB CHR bank at PPU $0400-$07FF (or $1400-$17FF)
  ||        $A: Select 1 KB CHR bank at PPU $0400-$07FF (or $1400-$17FF)
  ||        B: Select 1 KB CHR bank at PPU $0C00-$0FFF (or $1C00-$1FFF)
  ||        $B: Select 1 KB CHR bank at PPU $0C00-$0FFF (or $1C00-$1FFF)
  |+-------- PRG A14 inversion
  |+-------- Invert PRG A14
  +--------- CHR A12 inversion
  +--------- Invert CHR A12
Power-on values:
* Standard MMC3 Registers $0-$7: $00, $02, $04, $05, $06, $07, $00, $01
* Extended MMC3 Registers $8-$B: $FE, $FF, $FF, $FF


==Variants==
=Solder Pad=
No submappers have been assigned yet for incompatible variants of the hardware.
The address mask in the $5000-$5FFF range is determined by the solder pad setting:
===0: Normal===
Pad setting  Address mask
Powers up with the PRG Base Register set to $00, causing the FK23C to mimic a standard MMC3, which means that the 8 KiB bank in CPU space at $E000 is the bank that ends the first 512 KiB ($7E000), even if the ROM image is larger than that.
-----------  ------------
===1: Extra PRG for multicart menu===
0            $5013
A few multicarts hold four 128 KiB PRG-ROM-bearing games with no space left in those 512 KiB for the multicart menu. The menu is then put into a separate 32 KiB PRG bank that is mapped into the full PRG address space as the end of a second 512 KiB PRG-ROM bank, the other 480 KiB of that second 512 KiB PRG-ROM bank being empty. Carts in that configuration thus boot up with the 8 KiB bank in CPU space at $E000 being the bank that ends the second 512 KiB ($FE000), by initializing the PRG Base Register to $60 (or $20). These carts can be automatically detected by the fact that they, and only they, all have 1024 KiB of PRG-ROM and 1024 KiB of CHR-ROM.
1            $5023
===2: Flipped MMC3 Registers $46 and $47===
2            $5043
For unknown reasons, the two very large (16 MiB of PRG-ROM) multicarts swap MMC3 registers $46 and $47, but not $06 and $07. Individual MMC3 games, such as Kage, on these multicarts were modified to account for this. These carts can be automatically detected by the fact that they contain 16384 KiB of PRG-ROM.
3            $5083
4            $5103
5            $5203
6            $5403
7            $5803
* A solder pad setting of zero (address mask $5013) will produce a usable result for any ROM image.
* Some multicarts only display their menu at settings other than 0.


==Notes==
=Protection (Submapper 2 only)=
* The RAM Configuration Register is not just enabled by Waixing games, but also by some of the later FK23C multicarts, which does not imply however that they are actually equipped with PRG-RAM.
Later Waixing games (and re-releases of earlier games) use the RAM Configuration Register for copy-protection purposes:
* If the RAM Configuration Register is enabled ''and'' the cart has non-volative PRG-RAM, then the PRG-RAM is always 32 KiB in size, and banks 1 and 3 are non-volatile.
* Write $A1 to $A001: Address range $5000-$5FFF to second half of 8 KiB WRAM bank 2, mapper registers there are disabled.
* If a cart has both CHR-ROM and CHR-RAM, then a NES 2.0 header must be used to specify that, as most emulators disable CHR-RAM completely if a NES 1.0 header with CHR-ROM is found.
* Write three values to $5000, $5010 and $5013.
* Large multicarts with no CHR-ROM use large amounts of CHR-RAM into which an individual game's CHR data is copied when it is selected. CHR-RAM sizes range from 64 KiB (10-in-1 Omake Game) to 128 KiB (150-in-1 Real Game, 245-in-1 Real Game) and even 256 KiB (120-in-1 Waixing Games).
* Do further initialization.
* Many Waixing games in GoodNES 3.23b that correctly should be set to mapper 176 are incorrectly set to [[INES Mapper 030|Mapper 30]]. These games were converted from Waixing's proprietary (and encrypted) .WXN format; the Mapper 30 designation is the result of interpreting these .WXN files' non-iNES header as if it were an iNES header. Some of them have already been hacked (or "fixed", bearing an "[f1]" tag) to remove the protection check described above.
* Write $E2 to $A001. Mapper registers in address range $5000-$5FFF; WRAM at CPU $6000-$7FFF points to 8 KiB WRAM bank 2.
* The ROM that GoodNES 3.23b calls "Mortal Kombat Trilogy - 8 People (M1274) (Ch) [!].zip" is commonly set to Mapper 176 even though it does not use FK23C-compatible register addresses and content.
* Copy 20 bytes from $7000 to $6000.
* The WXN version of ''帝国风暴 (Dìguó Fēngbào) - Napoleon's War'' requires PAL or Dendy timing. On NTSC systems, the game will freeze before the main game screen is shown because of an excessively long NMI handler. The game will ''appear'' to run even in NTSC mode on some emulators that do not emulate the RAM Configuration Register and instead interpret the $E0 write to $A001 to mean "deny any writes to WRAM". The game map will be empty in those emulators, rendering the game unplayable.
* Copy and XOR bytes from $6000, $6010 and $6013 to $0100-$0102.
* The game ''星河战士 (Xīnghé Zhànshì)'', which is a variant of Waixing's ''外星戰士 (Wàixīng Zhànshì)'', relies on MMC3 registers #0-7 being initialized to 0/2/4/5/6/7/0/1 after a reset.
* Execute code at CPU $0100.
Hacked ROMs can be detected by them writing to $5000/$5010/$5013 but then no longer jumping to $0100.
=See also=
* [[NES 2.0 Mapper 523]] is a variant of this mapper with hard-wired mirroring that connects CHR-ROM differently to produce 4/2 KiB instead of 2/1 KiB banks.

Latest revision as of 18:48, 17 December 2021

iNES Mapper 176 denotes the 8025 enhanced MMC3 chipset. It used by many multicarts, Chinese single-game and educational computer cartridges, and Techno Source's Intellivision X2 Plug-and-Play console. Incompatible variations exist that are denoted via NES 2.0 Submapper.

Submappers
# PCB codes UNIF MAPR MMC3 Outer bank registers Example
Ext. mode PRG bits $46/47 1SM Extra WRAM Address mask PRG A21+ CHR A21+ CNROM latch
0 LP-8002KB, SFC-12B BMC-Super24in1SC03 - 6 normal - - $Fxx3 - - - YH-xxx multicarts, Rockman 6-in-1
1 FK-xxx/BS-xxx BMC-FK23C/BMC-FK23CA $5FF3.1 8 normal - - $Fxx3 - - yes FK-xxxx multicarts
2 FS005/FS006 WAIXING-FS005 $5FF3.1 6 swapped yes $A001.0-1 $Fxx3 $5xx0.3/7, $5xx2.6-7/5 - - Waixing 2005+ re-releases, 245-in-1 Real Game
3 JX9003B - - 8 normal - - $Fxx7 $5xx5 $5xx6 - Super Mario 160-in-1 Funny Time
4 ? - - 6 normal - - $Fxx3 $5xx2.7 - - GameStar Smart Genius Deluxe
5 HST-162 - - 6 normal - - $Fxx3 $4800 - - Game 500-in-1
  • The SFC-12B PCB (submapper 0) mounts both CHR-ROM and CHR-RAM that are selected via $5xx0.5.
  • Eight MMC3 PRG bits mean that bit 6 and 7 of $8000.6/7 are applied, and the fixed banks are $FE/$FF rather than $3E/$3F. This implies that the multicart's reset vector lies at address PRG-ROM address $1FFFFC rather than $7FFFC if the PRG-ROM is that large.

Registers

FS005 (Submapper 2) can disable the registers in the $5000-$5FFF range using the RAM Configuration Register ($A001). The same register also enables a mixed CHR-ROM/CHR-RAM mode that is similar to INES Mapper 195.

Mode Register ($5xx0)

Mask: $Fxx7 (Submapper 3), $5xx3 (all others), x determined by solder pad setting 

7654 3210
---- ----
PCTm PMMM
|||| ||||
|||| |+++- Select PRG Banking Mode (ignored in Extended MMC3 Mode)
|||| |      0: MMC3 PRG Mode, 2 MiB/512 KiB Outer PRG Bank Size
|||| |      1: MMC3 PRG Mode, 256 KiB Outer PRG Bank Size
|||| |      2: MMC3 PRG Mode, 128 KiB Outer PRG Bank Size
|||| |      3: NROM-128 PRG Mode, 16 KiB PRG at $8000-$BFFF mirrored at $C000-$FFFF
|||| |      4: NROM-256 PRG Mode, 32 KiB PRG at $8000-$FFFF
|||| |      5: UNROM PRG Mode, 16 KiB PRG at $8000-$BFFF, inner bank #7 at $C000-$FFFF
|||| |      6-7: Never used
|||| +---- PRG A21 (Submapper 2 only)
|||+------ Select Outer CHR Bank Size
|||         0: In MMC3 CHR Mode: 256 KiB
|||            In CNROM CHR Mode: 32 KiB (Submapper 1 only)
|||         1: In MMC3 CHR Mode: 128 KiB
|||            In CNROM CHR Mode: 16 KiB (Submapper 1 only)
||+------- Submappers 0/1 with both CHR-ROM and CHR-RAM (e.g. SFC-12B PCB):
||          0: Select CHR-ROM
||          1: Select CHR-RAM
||         Submapper 1 with $5xx0.6=1:
||          0: Enable CNROM latch (CNROM mode)
||          1: Disable CNROM latch (NROM mode)
|+-------- CHR A10-12 Mode
|           0: from MMC3
|           1: from PPU
+--------- PRG A22 (Submapper 2 only)

Power-on value: $00

PRG Base Register LSB ($5xx1)

Mask: $Fxx7 (Submapper 3), $Fxx3 (all others), x determined by solder pad setting 

7654 3210
---- ----
.PPP PPPP
 ||| ||||
 +++-++++- PRG A20..A14

Power-on value: $00

Depending on the PRG banking mode set via $5xx0, only the higher bits of this register are applied: 

PRG A..
21111111
09876543
--------
MMMMMMMM  Submappers 1/3 in PRG Mode 0 (MMC3 2 MiB) or Extended MMC3 Mode
BBMMMMMM  Submappers 0/2/4 in PRG Mode 0 (MMC3 512 KiB)
BBBMMMMM  PRG Mode 1 (MMC3 256 KiB)
BBBBMMMM  PRG Mode 2 (MMC3 128 KiB)
BBBBBBBC  PRG Mode 3 (NROM-128)
BBBBBBCC  PRG Mode 4 (NROM-256)
BBBBLLLC  PRG Mode 5 (UNROM)

M: Bit comes from MMC3 ($8000.6/7 or fixed bank)
B: Bit comes from PRG Base Register ($5xx1)
L: Bit comes from UNROM Latch ($8000-$FFFF or fixed bank)
C: Bit comes from CPU

Submapper 5 only selects PRG A14-A18 (i.e. 512 KiB) via this register, selecting upper PRG bits via register $4800.

PRG Base Register MSB ($5xx5), Submapper 3 only

Mask: $Fxx7 (Submapper 3), x determined by solder pad setting 

7654 3210
---- ----
.... PPPP
     ||||
     ++++- PRG Base A24..A21

Power-on value: $00

PRG Base Register MSB ($4800), Submapper 5 only

Mask: $F800 

7654 3210
---- ----
..PP PPPP
  || ||||
  ++-++++- PRG Base A24..A19

Power-on value: $00

CHR Base Register LSB ($5xx2)

Mask: $Fxx7 (Submapper 3), $5xx3 (all others), x determined by solder pad setting 

7654 3210
---- ----
ccdC CCCC
|||| ||||
++++-++++- CHR A20..A13
||+------- PRG A25 (Submapper 2 only)
++-------- PRG A24..A23 (Submapper 2 only)
+--------- PRG A21 (Submapper 4)

Power-on value: $00

Depending on the CHR banking mode set via $5xx0, only the higher bits of this register are applied: 

CHR A..
21111111111
09876543210
-----------
BBBMMMMMMMM  MMC3 CHR Mode ($5xx0.6=0), 256 KiB ($5xx0.4=0)
BBBBMMMMMMM  MMC3 CHR Mode ($5xx0.6=0), 128 KiB ($5xx0.4=1)
BBBBBBLLPPP  CNROM CHR Mode ($5xx0.6=1, $5xx0.5=0), 32 KiB ($5xx0.4=0), Submapper 1 only
BBBBBBBLPPP  CNROM CHR Mode ($5xx0.6=1, $5xx0.5=0), 16 KiB ($5xx0.4=1), Submapper 1 only
BBBBBBBBPPP  NROM CHR Mode ($5xx0.6=1, $5xx0.5=1 or Submapper other than 1)

M: Bit comes from MMC3 ($8000.0-5)
B: Bit comes from CHR Base Register ($5xx2)
L: Bit comes from CNROM Latch ($8000-$FFFF)
P: Bit comes from PPU

CHR Base Register MSB ($5xx6), Submapper 3 only

Mask: $Fxx7 (Submapper 3), x determined by solder pad setting 

7654 3210
---- ----
.... PPPP
     ||||
     ++++- CHR Base A24..A21

Power-on value: $00

Extended Mode Register ($5xx3), Submappers 1-2 only

Mask: $Fxx3, x determined by solder pad setting 

7654 3210
---- ----
.?.. .?E.
       | 
       +- Extended MMC3 Mode
           0: disable
           1: enable

Power-on value: $00

Most multicarts write value $44 rather than $00 to disable Extended MMC3 Mode. Hardware tests do not indicate any difference in behavior between writing $00 and $44.

Mirroring Register ($A000)

Mask: $E003

7654 3210
---- ----
.... ..MM
       ++- Select nametable mirroring 
           0: Vertical
           1: Horizontal
           2: Single-screen, page 0 (Submapper 2 only)
           3: Single-screen, page 1 (Submapper 2 only)
Power-on value: $00

Single-screen mirroring is only available when the RAM Configuration Register is enabled ($A001.5).

RAM Configuration Register ($A001), Submapper 2 only

Mask: $E003

This register functions like MMC3 register $A001 until bit 5 is set, which turns it into the RAM Configuration Register. 

7654 3210
---- ----
RFE. SCWW
|||  ||||
|||  ||++- Select 8 KiB PRG-RAM bank at $6000-$7FFF. Ignored if Bit 5 is clear.
|||  |+--- Select the memory type in the first 8 KiB of CHR space. Ignored if Bit 5 is clear.
|||  |      0: First 8 KiB are CHR-ROM
|||  |      1: First 8 KiB are CHR-RAM
|||  +---- Unknown
||+------- RAM Configuration Register Enable
||          0: RAM Configuration Register disabled, $A001 functions as on MMC3, 8 KiB of WRAM
||          1: RAM Configuration Register enabled, 32 KiB of WRAM
|+-------- Outer Bank Registers Enable. Ignored if Bit 5 is clear.
|           0: Outer Bank Registers disabled, $5000-$5FFF maps to the second 4 KiB of the 8 KiB WRAM bank 2
|           1: Outer Bank Registers enabled in the $5000-$5FFF range
+--------- PRG RAM enable (0: disable, 1: enable)

Power-on value: $00

UNROM latch ($8000-$FFFF)

In UNROM Mode (PRG Mode 5), writing to this address range changes the 16 KiB inner PRG bank at $8000-$BFFF.

CNROM latch ($8000-$FFFF), Submapper 1 only

In CNROM Mode, writing to this address range changes the inner CHR bank.

MMC3-compatible registers, Extended MMC3 Mode ($8000/$8001, $C000/$C001, $E000/$E001)

Mask: $E003 (verified on real hardware)

Some multicart games depend on writes to $9FFF not doing anything as a result of the MMC3 address mask being $E003 rather than the standard $E001.

If the "Extended MMC3 Mode" bit in register $5xx3 is clear, then these registers function identically to the MMC3. On Submappers 1 and 2, if the "Extended MMC3 Mode" bit is set, four more bank registers become available at $8000/$8001, so that the original two 2 KiB CHR banks become four 1 KiB CHR banks, and the two fixed 8 KiB PRG banks become selectable, similar to the RAMBO-1. Register $8000 if $5xx3 bit 1 is set: 

7  bit  0
---- ----
CP.. RRRR
||   ||||
||   ++++- Specify which bank register to update on next write to Bank Data register
||         $0: Select 1 KB CHR bank at PPU $0000-$03FF (or $1000-$13FF)
||         $1: Select 1 KB CHR bank at PPU $0800-$0BFF (or $1800-$1BFF)
||         $2: Select 1 KB CHR bank at PPU $1000-$13FF (or $0000-$03FF)
||         $3: Select 1 KB CHR bank at PPU $1400-$17FF (or $0400-$07FF)
||         $4: Select 1 KB CHR bank at PPU $1800-$1BFF (or $0800-$0BFF)
||         $5: Select 1 KB CHR bank at PPU $1C00-$1FFF (or $0C00-$0FFF)
||         $6: Select 8 KB PRG ROM bank at $8000-$9FFF (or $C000-$DFFF)
||         $7: Select 8 KB PRG ROM bank at $A000-$BFFF
||         $8: Select 8 KB PRG ROM bank at $C000-$DFFF (or $8000-$9FFF)
||         $9: Select 8 KB PRG ROM bank at $E000-$FFFF
||         $A: Select 1 KB CHR bank at PPU $0400-$07FF (or $1400-$17FF)
||         $B: Select 1 KB CHR bank at PPU $0C00-$0FFF (or $1C00-$1FFF)
|+-------- Invert PRG A14
+--------- Invert CHR A12

Power-on values:
* Standard MMC3 Registers $0-$7: $00, $02, $04, $05, $06, $07, $00, $01
* Extended MMC3 Registers $8-$B: $FE, $FF, $FF, $FF

Solder Pad

The address mask in the $5000-$5FFF range is determined by the solder pad setting: 

Pad setting  Address mask
-----------  ------------
0            $5013
1            $5023
2            $5043
3            $5083
4            $5103
5            $5203
6            $5403
7            $5803
  • A solder pad setting of zero (address mask $5013) will produce a usable result for any ROM image.
  • Some multicarts only display their menu at settings other than 0.

Protection (Submapper 2 only)

Later Waixing games (and re-releases of earlier games) use the RAM Configuration Register for copy-protection purposes:

  • Write $A1 to $A001: Address range $5000-$5FFF to second half of 8 KiB WRAM bank 2, mapper registers there are disabled.
  • Write three values to $5000, $5010 and $5013.
  • Do further initialization.
  • Write $E2 to $A001. Mapper registers in address range $5000-$5FFF; WRAM at CPU $6000-$7FFF points to 8 KiB WRAM bank 2.
  • Copy 20 bytes from $7000 to $6000.
  • Copy and XOR bytes from $6000, $6010 and $6013 to $0100-$0102.
  • Execute code at CPU $0100.

Hacked ROMs can be detected by them writing to $5000/$5010/$5013 but then no longer jumping to $0100.

See also

  • NES 2.0 Mapper 523 is a variant of this mapper with hard-wired mirroring that connects CHR-ROM differently to produce 4/2 KiB instead of 2/1 KiB banks.
Retrieved from "https://www.nesdev.org/w/index.php?title=INES_Mapper_176&oldid=18970"