INES Mapper 219: Difference between revisions

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{{DEFAULTSORT:219}} [[Category:iNES Mappers]] [[Category:Mappers with scanline IRQs]]
{{DEFAULTSORT:219}} [[Category:iNES Mappers]] [[Category:Mappers with scanline IRQs]]
[[iNES Mapper 219]], also known as "UNL A9746", is sort of like an [[MMC3]] without fixed banks, and some odd CHR banking.
iNES Mapper 219 is used for the 卡聖 (Kǎshèng) A9461 MMC3-clone-bearing board, used by:
==Banking==
* ''Toy Story''
*PRG: 4x8KiB (none fixed), 4 bits = 128KiB max
* ''Super 1997 4-in-1 (NT-8029)''
*CHR: 8x1KiB, 12 bits = 4MiB max


==Registers==
==Mode Register ($8002)==
  Mask: $E003
  Mask: $E003
$8000 Select Register 1
$8002 Select Register 2
$8001 Control Register
Whichever of $8000, $8002 is last written decides what $8001 writes do.
   
   
It appears to have [[MMC3#IRQ_latch_.28.24C000-.24DFFE.2C_even.29 | MMC3-like IRQ registers,]] as the implementation just falls through and uses those directly.
7654 3210
Mask $E001  
---------
  $C000 IRQ latch
CPMR RRRR
  $C001 IRQ reload
||++-++++-*Select bank register number (0-7 in MMC3 mode, $08-$26 in Extended mode)
  $E000 IRQ disable
||+------- Select mode
  $E001 IRQ enable
||          0: MMC3 mode
||          1: Extended mode
|+--------*1: PRG A14 inversion in MMC3 mode
+---------*1: CHR A12 inversion in MMC3 mode
* Same as $8000
==MMC3 mode registers ($8000-$FFFF)==
Mask: $E001
$A000, $A001, $C000, $C001, $E000, $E001: As on regular [[MMC3]].
 
==MMC3 Bank Register Index ($8000)/Data ($8001)==
Mask: $E001. Used only if $8002 bit 5=0, see [[MMC3]]. Note that PRG-ROM and CHR-ROM banks are masked to 128 KiB.
 
==Extended PRG-ROM Bank Index ($8000, $23-$26)/Data ($8001)==
Mask: $E001. Used only if $8002 bit 5=1.
 
$8000/$8002 value:
D~7654 3210
  ---------
  ..10 .RRR
        +++- 6: Select 8 KiB PRG-ROM bank at CPU $8000-$9FFF
              5: Select 8 KiB PRG-ROM bank at CPU $A000-$BFFF
              4: Select 8 KiB PRG-ROM bank at CPU $C000-$DFFF
              3: Select 8 KiB PRG-ROM bank at CPU $E000-$FFFF
     
$8001 value:
D~7654 3210
  ---------
  ..BB BB..
    ++-++--- Bits 0-3 (reversed order) of 8 KiB PRG-ROM bank number
 
==CHR-ROM Bank Number Latch Index ($8000, $08-$1E, even)/Data ($8001)==
Mask: $E001. Used only if $8002 bit 5=1.
 
$8000 value:
D~7654 3210
  ---------
  ..00 1..0
or
D~7654 3210
  ---------
  ..01 ...0
$8001 value:
D~7654 3210
  ---------
  .... .654
        +++- Bits 4-6 OR'd with next CHR-ROM switch's data
 
==CHR-ROM Pseudo 2 KiB switch Index ($8000, $09-$0F, odd)/Data ($8001)==
Mask: $E001. Used only if $8002 bit 5=1.
 
$8000 value:
D~7654 3210
  ---------
  ..00 1RR1
        ++-- Select CHR-ROM address range to switch
          |    0: PPU $0000-$03FF
          |    1: PPU $0400-$07FF
          |   2: PPU $0800-$0BFF
          |    3: PPU $0C00-$0FFF
          +-- OR'd with Bit 0 of CHR-ROM bank data
 
$8001 value:
D~7654 3210
  ---------
  BBBB BBB.
  ++++-+++-- Bits 0-6 of 1 KiB CHR-ROM bank number at PPU address selected via $8000/$8002.
The value is OR'd with bit 1 SHR 1 of the value written to $8000, then OR'd with bits 0-2 SHL 4 of the value written to the CHR-ROM latch.
 
==CHR-ROM 1 KiB switch Index ($8000, $11-$1F, odd)/Data ($8001)==
Mask: $E001. Used only if $8002 bit 5=1.
 
$8000 value:
  D~7654 3210
  ---------
  ..01 RR.1
        ++--- Select CHR-ROM address range to switch
              0: PPU $1000-$13FF
              1: PPU $1400-$17FF
              2: PPU $1800-$1BFF
              3: PPU $1C00-$1FFF
 
$8001 value:
D~7654 3210
  ---------
  BBBB BBB.
  ++++-+++-- Bits 0-6 of 1 KiB CHR-ROM bank number at PPU address selected via $8000/$8002.
The value is OR'd with bits 0-2 SHL 4 of the value written to the CHR-ROM latch.
 
==Outer Bank Bit 0 ($5002)==
  Mask: $5003
  D~7654 3210
  ---------
  .... ...B
          +- Bit 0 of 128 KiB outer PRG-ROM and CHR-ROM bank
 
==Outer Bank Bit 1 ($5003)==
  Mask: $5003
D~7654 3210
  ---------
  ..B. ....
    +------- Bit 1 of 128 KiB outer PRG-ROM and CHR-ROM bank


CHR banking is very odd. The following bits are ORed together:
The Outer Bank register must be initialized to $03 for the menu to appear.
Latch: CBA98765.... [write << 4]
Inner: .....7654321 [write >> 1]
and, if the bank is $0400 or $0C00, the least significant bit is further ORed with 1.
This has the effect of allowing consecutive writes to adjacent bank regs to get "sort of" a 2k bank. Nestopia also ANDs the least significant remaining bit with 0 for the $0000 and $0800 pages, thereby effectively setting it to A10 for the left pattern table ($0000-$0FFF), but the coding appears to also mask off bits 765 from the lower write in this operation. As they can be set by the latch anyway, it is unclear if this is intentional.


{| class="wikitable"
==Note==
| $8000 write || $8002 write || bits || $8000 effect
This mapper gets hot and breaks down easily when using dumping devices.
|-
| $26 || - || ..PPPP.. || (reversed) bits of PRG bank $8000-$9FFF, central nibble only
|-
| $25 || - || ..PPPP.. || (reversed) bits of PRG bank $A000-$BFFF, central nibble only
|-
| $24 || - || ..PPPP.. || (reversed) bits of PRG bank $C000-$DFFF, central nibble only
|-
| $23 || - || ..PPPP.. || (reversed) bits of PRG bank $E000-$FFFF, central nibble only
|-
| - || $08-$1e(even) || CBA98765 || Outer CHR bit latch for any 1k bank, 8 bits
|-
| - || $09 || 765432*. || Inner 7 CHR bits for $0000-$03FF (*least bit ANDed to 0? See above.)
|-
| - || $0B || 765432*. || Inner 7 CHR bits for $0400-$07FF (*least bit ORed to 1 regardless)
|-
| - || $0D || 765432*. || Inner 7 CHR bits for $0800-$0BFF (*least bit ANDed to 0? See above.)
|-
| - || $0F || 765432*. || Inner 7 CHR bits for $0C00-$0FFF (*least bit ORed to 1 regardless)
|-
| - || $11 || 7654321. || Inner 7 CHR bits for $1000-$13FF
|-
| - || $15 || 7654321. || Inner 7 CHR bits for $1400-$17FF
|-
| - || $19 || 7654321. || Inner 7 CHR bits for $1800-$1BFF
|-
| - || $1D || 7654321. || Inner 7 CHR bits for $1C00-$1FFF
|}


==Sources==
==Sources==
*[https://sourceforge.net/p/fceultra/code/3320/tree/fceu/trunk/src/boards/a9746.cpp FCEUX implementation]
*[https://sourceforge.net/p/fceultra/code/3320/tree/fceu/trunk/src/boards/a9746.cpp FCEUX implementation]
*[https://github.com/rdanbrook/nestopia/blob/88d130fd083b9662ef49e8d5ef95513f4bb8759e/source/core/board/NstBoardUnlA9746.cpp Nestopia's implementation]
*[https://github.com/rdanbrook/nestopia/blob/88d130fd083b9662ef49e8d5ef95513f4bb8759e/source/core/board/NstBoardUnlA9746.cpp Nestopia's implementation]

Latest revision as of 14:10, 25 March 2024

iNES Mapper 219 is used for the 卡聖 (Kǎshèng) A9461 MMC3-clone-bearing board, used by:

  • Toy Story
  • Super 1997 4-in-1 (NT-8029)

Mode Register ($8002)

Mask: $E003

7654 3210
---------
CPMR RRRR
||++-++++-*Select bank register number (0-7 in MMC3 mode, $08-$26 in Extended mode)
||+------- Select mode
||          0: MMC3 mode
||          1: Extended mode
|+--------*1: PRG A14 inversion in MMC3 mode
+---------*1: CHR A12 inversion in MMC3 mode

* Same as $8000

MMC3 mode registers ($8000-$FFFF)

Mask: $E001

$A000, $A001, $C000, $C001, $E000, $E001: As on regular MMC3.

MMC3 Bank Register Index ($8000)/Data ($8001)

Mask: $E001. Used only if $8002 bit 5=0, see MMC3. Note that PRG-ROM and CHR-ROM banks are masked to 128 KiB.

Extended PRG-ROM Bank Index ($8000, $23-$26)/Data ($8001)

Mask: $E001. Used only if $8002 bit 5=1.

$8000/$8002 value:

D~7654 3210
  ---------
  ..10 .RRR
        +++- 6: Select 8 KiB PRG-ROM bank at CPU $8000-$9FFF
             5: Select 8 KiB PRG-ROM bank at CPU $A000-$BFFF
             4: Select 8 KiB PRG-ROM bank at CPU $C000-$DFFF 
             3: Select 8 KiB PRG-ROM bank at CPU $E000-$FFFF

$8001 value:

D~7654 3210
  ---------
  ..BB BB..
    ++-++--- Bits 0-3 (reversed order) of 8 KiB PRG-ROM bank number

CHR-ROM Bank Number Latch Index ($8000, $08-$1E, even)/Data ($8001)

Mask: $E001. Used only if $8002 bit 5=1.

$8000 value:

D~7654 3210
  ---------
  ..00 1..0
or
D~7654 3210
  ---------
  ..01 ...0

$8001 value:

D~7654 3210
  ---------
  .... .654
        +++- Bits 4-6 OR'd with next CHR-ROM switch's data

CHR-ROM Pseudo 2 KiB switch Index ($8000, $09-$0F, odd)/Data ($8001)

Mask: $E001. Used only if $8002 bit 5=1.

$8000 value:

D~7654 3210
  ---------
  ..00 1RR1
        ++-- Select CHR-ROM address range to switch
         |    0: PPU $0000-$03FF
         |    1: PPU $0400-$07FF
         |    2: PPU $0800-$0BFF
         |    3: PPU $0C00-$0FFF
         +-- OR'd with Bit 0 of CHR-ROM bank data

$8001 value:

D~7654 3210
  ---------
  BBBB BBB.
  ++++-+++-- Bits 0-6 of 1 KiB CHR-ROM bank number at PPU address selected via $8000/$8002.

The value is OR'd with bit 1 SHR 1 of the value written to $8000, then OR'd with bits 0-2 SHL 4 of the value written to the CHR-ROM latch.

CHR-ROM 1 KiB switch Index ($8000, $11-$1F, odd)/Data ($8001)

Mask: $E001. Used only if $8002 bit 5=1.

$8000 value:

D~7654 3210
  ---------
  ..01 RR.1
       ++--- Select CHR-ROM address range to switch
              0: PPU $1000-$13FF
              1: PPU $1400-$17FF
              2: PPU $1800-$1BFF
              3: PPU $1C00-$1FFF

$8001 value:

D~7654 3210
  ---------
  BBBB BBB.
  ++++-+++-- Bits 0-6 of 1 KiB CHR-ROM bank number at PPU address selected via $8000/$8002.

The value is OR'd with bits 0-2 SHL 4 of the value written to the CHR-ROM latch.

Outer Bank Bit 0 ($5002)

Mask: $5003

D~7654 3210
  ---------
  .... ...B
          +- Bit 0 of 128 KiB outer PRG-ROM and CHR-ROM bank

Outer Bank Bit 1 ($5003)

Mask: $5003

D~7654 3210
  ---------
  ..B. ....
    +------- Bit 1 of 128 KiB outer PRG-ROM and CHR-ROM bank

The Outer Bank register must be initialized to $03 for the menu to appear.

Note

This mapper gets hot and breaks down easily when using dumping devices.

Sources