INES Mapper 234: Difference between revisions
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[[Category:iNES Mappers]] | [[Category:iNES Mappers]][[Category:Multicart mappers]][[Category:in NesCartDB]][[Category:Discrete logic mappers]] | ||
Mapper 234 | [[iNES Mapper 234]] represents the Maxi 15 multicart, which allows the combination of slightly-modified 32k/32k [[CNROM]] and 64k/64k [[NINA-003-006|NINA-03]] games. The only instance of this board was released with 512k/512k, but seems to be laid out in a way that would support a total of 1M/1M in 4 512k ROMs. | ||
== Overview == | |||
* PRG ROM size: 512 KiB or 1MiB | |||
* PRG ROM bank size: 32 KiB inner / 32 or 64 KiB outer | |||
* PRG RAM: No | |||
* CHR capacity: 512 KiB or 1MiB ROM | |||
* CHR bank size: 8 KiB inner / 32 or 64 KiB outer | |||
* Nametable [[mirroring]]: Controlled by mapper. | |||
* Subject to [[bus conflict]]s: Yes | |||
== Registers == | |||
Typical for the Atari 2600, but strange for the NES: Registers lie at $FF80-$FFF7 but bankswitching happens on the ''value that was read''. Bus conflicts are thus avoided by storing the library of desired bankswitch values in ROM. Writes to the registers will produce bus conflicts. | |||
All registers are cleared on reset. | |||
=== Outer Bank Control ($FF80-$FF9F) === | |||
7 bit 0 | |||
MOQq BBBb | |||
││││ ││││ | |||
││││ └┴┴┴── Block selection | |||
│││└─────── ROMs 3+4 Disable (0=normal, 1=disable ROMs 3+4 even if selected by Q) | |||
││└──────── ROM switch (0=select ROMs 1+2, 1=select ROMs 3+4) | |||
│└───────── Mode (0=CNROM, 1=NINA-03) | |||
└────────── Mirroring (0=Vertical, 1=Horizontal) | |||
Since the cartridge was distributed with only ROMs 1+2 populated, the Q and q bits are irrelevant. | |||
The q bit seems to have been intended to have been an extra address line for ROMs 3+4, enabling a total of 1.5M/1.5M in the cartridge, but instead of just being routed to the A19 line for ROMs 3+4, it instead also is ORed with the Output Enable signal and so disables them. | |||
Once any of the Q, q, BBB, or b bits are set, neither this register nor the Lockout defeat register can be updated. | |||
=== Lockout defeat control ($FFC0-$FFDF) === | |||
7 bit 0 | |||
.... ..LL | |||
││ | |||
└┴── Lockout defeat (charge pump drive) | |||
=== Inner Bank Control ($FFE8-$FFF7) === | |||
7 bit 0 | |||
.cCC ...P | |||
│││ │ | |||
│││ └── PRG page | |||
└┴┴─────── CHR page | |||
When the outer bank control has been set to CNROM mode, the P and c bits are ignored, and QqBBBb select a 32kB slice of both PRG and CHR for the game to occupy. | |||
When the outer bank control has been set to NINA-03 mode, the b bit is ignored, and replaced with P and C for each ROM; thus the QqBBB bits select a 64kB slice for the game. | |||
Revision as of 21:41, 25 July 2012
iNES Mapper 234 represents the Maxi 15 multicart, which allows the combination of slightly-modified 32k/32k CNROM and 64k/64k NINA-03 games. The only instance of this board was released with 512k/512k, but seems to be laid out in a way that would support a total of 1M/1M in 4 512k ROMs.
Overview
- PRG ROM size: 512 KiB or 1MiB
- PRG ROM bank size: 32 KiB inner / 32 or 64 KiB outer
- PRG RAM: No
- CHR capacity: 512 KiB or 1MiB ROM
- CHR bank size: 8 KiB inner / 32 or 64 KiB outer
- Nametable mirroring: Controlled by mapper.
- Subject to bus conflicts: Yes
Registers
Typical for the Atari 2600, but strange for the NES: Registers lie at $FF80-$FFF7 but bankswitching happens on the value that was read. Bus conflicts are thus avoided by storing the library of desired bankswitch values in ROM. Writes to the registers will produce bus conflicts.
All registers are cleared on reset.
Outer Bank Control ($FF80-$FF9F)
7 bit 0 MOQq BBBb ││││ ││││ ││││ └┴┴┴── Block selection │││└─────── ROMs 3+4 Disable (0=normal, 1=disable ROMs 3+4 even if selected by Q) ││└──────── ROM switch (0=select ROMs 1+2, 1=select ROMs 3+4) │└───────── Mode (0=CNROM, 1=NINA-03) └────────── Mirroring (0=Vertical, 1=Horizontal)
Since the cartridge was distributed with only ROMs 1+2 populated, the Q and q bits are irrelevant.
The q bit seems to have been intended to have been an extra address line for ROMs 3+4, enabling a total of 1.5M/1.5M in the cartridge, but instead of just being routed to the A19 line for ROMs 3+4, it instead also is ORed with the Output Enable signal and so disables them.
Once any of the Q, q, BBB, or b bits are set, neither this register nor the Lockout defeat register can be updated.
Lockout defeat control ($FFC0-$FFDF)
7 bit 0
.... ..LL
││
└┴── Lockout defeat (charge pump drive)
Inner Bank Control ($FFE8-$FFF7)
7 bit 0 .cCC ...P │││ │ │││ └── PRG page └┴┴─────── CHR page
When the outer bank control has been set to CNROM mode, the P and c bits are ignored, and QqBBBb select a 32kB slice of both PRG and CHR for the game to occupy.
When the outer bank control has been set to NINA-03 mode, the b bit is ignored, and replaced with P and C for each ROM; thus the QqBBB bits select a 64kB slice for the game.
