Namco 163: Difference between revisions

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m (no, the mmc3/mmc4/ss5 had 44 pins. N163 &al had 48 pins.)
(information from bootgod (there isn't a separate chr-ram; the 163 can just use nametable ram as chr-ram))
Line 8: Line 8:
* PRG ROM bank size: 8 KB
* PRG ROM bank size: 8 KB
* PRG RAM: Up to 8 KB
* PRG RAM: Up to 8 KB
* CHR capacity: Up to 256 KB ROM and/or 32 KB RAM simultaneously [[Category:Mappers with CHR RAM]]
* CHR capacity: Up to 256 KB ROM (and/or 32 KB RAM simultaneously?) [[Category:Mappers with CHR RAM]]
* CHR bank size: 1 KB
* CHR bank size: 1 KB
* Nametable [[mirroring]]: Controlled by mapper (Mapper 19), hardwired (Mapper 210)
* Nametable [[mirroring]]: Controlled by mapper (Mapper 19), hardwired (Mapper 210)
Line 27: Line 27:
* PPU $1800-$1BFF: 1 KB switchable CHR bank
* PPU $1800-$1BFF: 1 KB switchable CHR bank
* PPU $1C00-$1FFF: 1 KB switchable CHR bank
* PPU $1C00-$1FFF: 1 KB switchable CHR bank
* PPU $2000-$23FF: 1 KB switchable CHR bank
* PPU $2400-$27FF: 1 KB switchable CHR bank
* PPU $2800-$2BFF: 1 KB switchable CHR bank
* PPU $2C00-$2FFF: 1 KB switchable CHR bank


== Registers ==
== Registers ==
Line 50: Line 54:
  +--------- IRQ Enable: (0: disabled; 1: enabled)
  +--------- IRQ Enable: (0: disabled; 1: enabled)


=== CHR Select 1…4 ($8000-$87FF,$8800,$9000,$9800) w ===
=== CHR and NT Select ($8000-$DFFF) w ===
{| class="wikitable"
{| class="wikitable"
! Write to CPU address !! 1KB CHR bank affected
! Value CPU writes !! Behavior
|-
|-
| $8000-$87FF || $0000-$03FF
| $00-$DF || Always selects 1KB page of CHR-ROM
|-
|-
| $8800-$8FFF || $0400-$07FF
| $E0-$FF || If enabled by bit in $E800 and using a N163 or N129, use the NES's internal nametables (even values for A, odd values for B)
|}
{| class="wikitable"
! Write to CPU address !! 1KB CHR bank affected !! Values ≥ $E0 denote NES NTRAM if
|-
|-
| $9000-$97FF || $0800-$0BFF
| $8000-$87FF || $0000-$03FF || $E800.6 = 0
|-
|-
| $9800-$9FFF || $0C00-$0FFF
| $8800-$8FFF || $0400-$07FF || $E800.6 = 0
|}
'''Note:''' Only on Mapper 19 = Namco 129/163, pages $E0-$FF are CHR-RAM, as long as [[Namco 163#PRG_Select_2_.2F_CHR-RAM_Enable_.28.24E800-.24EFFF.29_w|$E800]].'''6''' is set to 0. If $E800.'''6''' is set to 1, then pages $E0-$FF refer to the last $20 pages of CHR-ROM as you'd expect.
 
=== CHR Select 5…8 ($A000-$A7FF,$A800,$B000,$B800) w ===
{| class="wikitable"
! Write to CPU address !! 1KB CHR bank affected
|-
|-
| $A000-$A7FF || $1000-$13FF
| $9000-$97FF || $0800-$0BFF || $E800.6 = 0
|-
|-
| $A800-$AFFF || $1400-$17FF
| $9800-$9FFF || $0C00-$0FFF || $E800.6 = 0
|-
|-
| $B000-$B7FF || $1800-$1BFF
| $A000-$A7FF || $1000-$13FF || $E800.7 = 0
|-
|-
| $B800-$BFFF || $1C00-$1FFF
| $A800-$AFFF || $1400-$17FF || $E800.7 = 0
|}
'''Note:''' Only on Mapper 19 = Namco 129/163, pages $E0-$FF are CHR-RAM, as long as [[Namco 163#PRG_Select_2_.2F_CHR-RAM_Enable_.28.24E800-.24EFFF.29_w|$E800]].'''7''' is set to 0. If $E800.'''7''' is set to 1, then pages $E0-$FF refer to the last $20 pages of CHR-ROM as you'd expect.
 
=== Nametable Select 1…4 ($C000-$C7FF,$C800,$D000,$D800) w (Namco 129,163 only) ===
{| class="wikitable"
! Write to CPU address !! 1KB nametable affected
|-
|-
| $C000-$C7FF || $2000-$23FF
| $B000-$B7FF || $1800-$1BFF || $E800.7 = 0
|-
|-
| $C800-$CFFF || $2400-$27FF
| $B800-$BFFF || $1C00-$1FFF || $E800.7 = 0
|-
|-
| $D000-$D7FF || $2800-$2BFF
| $C000-$C7FF || $2000-$23FF || always
|-
|-
| $D800-$DFFF || $2C00-$2FFF
| $C800-$CFFF || $2400-$27FF || always
|}
{| class="wikitable"
! Value CPU writes !! Behavior
|-
|-
| $00-$DF || Use a 1KB page of CHR-ROM as a nametable
| $D000-$D7FF || $2800-$2BFF || always
|-
|-
| $E0-$FF || Use the NES's internal nametables (even values for A, odd values for B)
| $D800-$DFFF || $2C00-$2FFF || always
|}
|}
'''Note:''' With mapper 210, a.k.a. Namco 175 or 340, these nametable selection registers have no effect.
'''Note:''' With mapper 210, a.k.a. Namco 175 or 340, the nametable selection registers have no effect, and nametable RAM cannot be used as CHR-RAM.
 
It is believed, but untested, that a game could add a normal SRAM and use it instead of the nametable RAM; if so, a game would be able to get 4-screen mirroring and many more pages of CHR-RAM.


=== External PRG RAM enable ($C000-$C7FF) w (Namco 175 only) ===
=== External PRG RAM enable ($C000-$C7FF) w (Namco 175 only) ===
Line 126: Line 120:
  ||++-++++- Select 8KB page of PRG-ROM at $A000
  ||++-++++- Select 8KB page of PRG-ROM at $A000
  |+-------- Disable CHR-RAM at $0000-$0FFF (Namco 129, 163 only)
  |+-------- Disable CHR-RAM at $0000-$0FFF (Namco 129, 163 only)
  |            0: Pages $E0-$FF are CHR-RAM
  |            0: Pages $E0-$FF use NT RAM as CHR-RAM
  |            1: Pages $E0-$FF are the last $20 banks of CHR-ROM)
  |            1: Pages $E0-$FF are the last $20 banks of CHR-ROM)
  +--------- Disable CHR-RAM at $1000-$1FFF (Namco 129, 163 only)
  +--------- Disable CHR-RAM at $1000-$1FFF (Namco 129, 163 only)
               0: Pages $E0-$FF are CHR-RAM
               0: Pages $E0-$FF use NT RAM as CHR-RAM
               1: Pages $E0-$FF are the last $20 banks of CHR-ROM)
               1: Pages $E0-$FF are the last $20 banks of CHR-ROM)


Revision as of 04:16, 28 February 2013

The Namco 129 and 163 with expansion sound are assigned to iNES Mapper 19, while simpler variants using the Namco 175 and 340 ICs have simpler mirroring and are assigned to iNES Mapper 210. All four were packaged in 48-pin TQFPs.

Many older programs incorrectly identify this mapper by the name Namco 106. Some sources use the name Namcot instead of Namco, as some games and PCBs use this variation on the company name.

Overview

  • PRG ROM size: Up to 512 KB
  • PRG ROM bank size: 8 KB
  • PRG RAM: Up to 8 KB
  • CHR capacity: Up to 256 KB ROM (and/or 32 KB RAM simultaneously?)
  • CHR bank size: 1 KB
  • Nametable mirroring: Controlled by mapper (Mapper 19), hardwired (Mapper 210)
  • Subject to bus conflicts: No

Banks

  • CPU $6000-$7FFF: 8 KB PRG RAM bank
  • CPU $8000-$9FFF: 8 KB switchable PRG ROM bank
  • CPU $A000-$BFFF: 8 KB switchable PRG ROM bank
  • CPU $C000-$DFFF: 8 KB switchable PRG ROM bank
  • CPU $E000-$FFFF: 8 KB PRG ROM bank, fixed to the last bank
  • PPU $0000-$03FF: 1 KB switchable CHR bank
  • PPU $0400-$07FF: 1 KB switchable CHR bank
  • PPU $0800-$0BFF: 1 KB switchable CHR bank
  • PPU $0C00-$0FFF: 1 KB switchable CHR bank
  • PPU $1000-$13FF: 1 KB switchable CHR bank
  • PPU $1400-$17FF: 1 KB switchable CHR bank
  • PPU $1800-$1BFF: 1 KB switchable CHR bank
  • PPU $1C00-$1FFF: 1 KB switchable CHR bank
  • PPU $2000-$23FF: 1 KB switchable CHR bank
  • PPU $2400-$27FF: 1 KB switchable CHR bank
  • PPU $2800-$2BFF: 1 KB switchable CHR bank
  • PPU $2C00-$2FFF: 1 KB switchable CHR bank

Registers

The 163 has 19 registers within $4800-$5FFF and $8000-$FFFF, while the the 175 and 340 only have 12. Each register occupies a range of $800 bytes, so $4800-$4FFF all refers to one register, $5000-$57FF all refers to another register, and so on.

Sound Data Port ($4800-$4FFF) r/w (Namco 129,163 only)

See Namco 163 audio.

IRQ Counter (low) ($5000-$57FF) r/w (Namco 129,163 only)

7  bit  0
---- ----
IIII IIII
|||| ||||
++++-++++- Low 8 bits of IRQ counter

IRQ Counter (high) / IRQ Enable ($5800-$5FFF) r/w (Namco 129,163 only)

7  bit  0
---- ----
EIII IIII
|||| ||||
|+++-++++- High 7 bits of IRQ counter
+--------- IRQ Enable: (0: disabled; 1: enabled)

CHR and NT Select ($8000-$DFFF) w

Value CPU writes Behavior
$00-$DF Always selects 1KB page of CHR-ROM
$E0-$FF If enabled by bit in $E800 and using a N163 or N129, use the NES's internal nametables (even values for A, odd values for B)
Write to CPU address 1KB CHR bank affected Values ≥ $E0 denote NES NTRAM if
$8000-$87FF $0000-$03FF $E800.6 = 0
$8800-$8FFF $0400-$07FF $E800.6 = 0
$9000-$97FF $0800-$0BFF $E800.6 = 0
$9800-$9FFF $0C00-$0FFF $E800.6 = 0
$A000-$A7FF $1000-$13FF $E800.7 = 0
$A800-$AFFF $1400-$17FF $E800.7 = 0
$B000-$B7FF $1800-$1BFF $E800.7 = 0
$B800-$BFFF $1C00-$1FFF $E800.7 = 0
$C000-$C7FF $2000-$23FF always
$C800-$CFFF $2400-$27FF always
$D000-$D7FF $2800-$2BFF always
$D800-$DFFF $2C00-$2FFF always

Note: With mapper 210, a.k.a. Namco 175 or 340, the nametable selection registers have no effect, and nametable RAM cannot be used as CHR-RAM.

It is believed, but untested, that a game could add a normal SRAM and use it instead of the nametable RAM; if so, a game would be able to get 4-screen mirroring and many more pages of CHR-RAM.

External PRG RAM enable ($C000-$C7FF) w (Namco 175 only)

7  bit  0
---- ----
.... ...E
        |
        +- 1: Enable PRG RAM

PRG Select 1 ($E000-$E7FF) w

7  bit  0
---- ----
MMPP PPPP
|||| ||||
||++-++++- Select 8KB page of PRG-ROM at $8000
|+-------- Namco 129, 163 only: Disable sound if set
++-------- Namco 340 only: Select mirroring
             0: One-screen A
             1: Vertical
             2: Horizontal
             3: One-screen B

PRG Select 2 / CHR-RAM Enable ($E800-$EFFF) w

7  bit  0
---- ----
HLPP PPPP
|||| ||||
||++-++++- Select 8KB page of PRG-ROM at $A000
|+-------- Disable CHR-RAM at $0000-$0FFF (Namco 129, 163 only)
|            0: Pages $E0-$FF use NT RAM as CHR-RAM
|            1: Pages $E0-$FF are the last $20 banks of CHR-ROM)
+--------- Disable CHR-RAM at $1000-$1FFF (Namco 129, 163 only)
             0: Pages $E0-$FF use NT RAM as CHR-RAM
             1: Pages $E0-$FF are the last $20 banks of CHR-ROM)

PRG Select 3 ($F000-$F7FF) w

7  bit  0
---- ----
..PP PPPP
  || ||||
  ++-++++- Select 8KB page of PRG-ROM at $C000

Write Protect for External RAM AND Sound Address Port ($F800-$FFFF) w (Namco 129, 163 only)

7  bit  0
---- ----
KKKK DCBA
|||| ||||
|||| |||+- 1: Write-protect 2kB window of external RAM from $6000-$67FF (0: write enable)
|||| ||+-- 1: Write-protect 2kB window of external RAM from $6800-$6FFF (0: write enable)
|||| |+--- 1: Write-protect 2kB window of external RAM from $7000-$77FF (0: write enable)
|||| +---- 1: Write-protect 2kB window of external RAM from $7800-$7FFF (0: write enable)
++++------ Must = b0100 to enable writes

Also see Namco 163 audio.

IRQ Operation

The IRQ is a 15-bit CPU cycle up-counter. $5000 and $5800 provide direct access to the counter itself (i.e., this isn't a reload value). Games can read and write to these registers in realtime.

The IRQ counter increments on each CPU cycle. Upon reaching $7FFF, an IRQ is fired, and it stops counting. Reading/Writing to $5000 or $5800 will acknowledge any pending IRQs.

References

All of the below are in Japanese:

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