PPU memory map: Difference between revisions

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(this is not VRAM, though it is the default mapping)
(Clarifying cartridge-mapping vs PPU-mapping.)
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* R = Mirror of $2000-2EFF (N)
* R = Mirror of $2000-2EFF (N)


(Note: All of this, with the exception of the palette, can be rewired in the cartridge. However, their function remains what is listed above even if rewired.)
== Hardware mapping ==
 
The mappings above are the fixed addresses from which the PPU uses to fetch data during rendering. The actual device that the PPU fetches data from, however, may be configured by the cartridge.
 
* $0000-1FFF is normally mapped by the cartridge to a [[CHR ROM vs. CHR RAM|CHR-ROM or CHR-RAM]], often with a bank switching mechanism.
 
* $2000-2FFF is normally mapped to the 2kb NES internal VRAM, providing 2 nametables with a [mirroring|Mirroring#Nametable_Mirroring]] configuration controlled by the cartridge, but it can be partly or fully remapped to RAM on the cartridge, allowing up to 4 simultaneous nametables.
 
* $3F00-3FFF is not configurable, always mapped to the internal palette control.

Revision as of 21:11, 19 January 2015

PPU memory map

The PPU addresses a 16k space, $0000-3FFF, completely separate from the CPU's data bus. It is either directly accessed by the PPU itself, or via the CPU with memory mapped registers at $2006 and $2007.

The NES has 2k of RAM dedicated to the PPU, normally mapped to the nametable address space from $2000-2FFF, but this can be rerouted through custom cartridge wiring.

Address range Size Description
$0000-$0FFF $1000 Pattern Table 0 [lower CHR bank]
$1000-$1FFF $1000 Pattern Table 1 [upper CHR bank]
$2000-$23FF $0400 Name Table #0
$2400-$27FF $0400 Name Table #1
$2800-$2BFF $0400 Name Table #2
$2C00-$2FFF $0400 Name Table #3
$3000-$3EFF $0F00 Mirrors of $2000-$2EFF
$3F00-$3F1F $0020 Palette RAM indexes [not RGB values]
$3F20-$3FFF $00E0 Mirrors of $3F00-$3F1F

In addition, the PPU contains 256 bytes of memory known as Object Attribute Memory in a separate address space, which determines how sprites are rendered. The CPU also manipulates this memory through special memory-mapped registers in its own address space.

Nametable layout

Address Size Note Description
$0000 $1000 C Pattern Table #0
$1000 $1000 C Pattern Table #1
$2000 $03C0 Name Table #0
$23C0 $0040 Attribute Table #0
$2400 $03C0 N Name Table #1
$27C0 $0040 N Attribute Table #1
$2800 $03C0 N Name Table #2
$2BC0 $0040 N Attribute Table #2
$2C00 $03C0 N Name Table #3
$2FC0 $0040 N Attribute Table #3
$3000 $0F00 R
$3F00 $0010 Background palette
$3F10 $0010 Sprite palette
$3F20 $00E0 P
  • C = This memory is not in the NES but on the cartridge board. It can be CHR ROM or CHR RAM.
  • N = Mirrored nametables, in a manner controlled by the cartridge board (see Mirroring)
  • P = Palette mirror
  • R = Mirror of $2000-2EFF (N)

Hardware mapping

The mappings above are the fixed addresses from which the PPU uses to fetch data during rendering. The actual device that the PPU fetches data from, however, may be configured by the cartridge.

  • $0000-1FFF is normally mapped by the cartridge to a CHR-ROM or CHR-RAM, often with a bank switching mechanism.
  • $2000-2FFF is normally mapped to the 2kb NES internal VRAM, providing 2 nametables with a [mirroring|Mirroring#Nametable_Mirroring]] configuration controlled by the cartridge, but it can be partly or fully remapped to RAM on the cartridge, allowing up to 4 simultaneous nametables.
  • $3F00-3FFF is not configurable, always mapped to the internal palette control.