PPU memory map: Difference between revisions

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($3000-$3F00 is unused by PPU, it as a mirror of $2000-$2F00 if the cartridge maps it that way)
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=== PPU memory map ===
=== PPU memory map ===


The [[PPU]] addresses a 14-bit (16kB) address space, $0000-3FFF, completely separate from the CPU's address bus. It is either directly accessed by the PPU itself, or via the CPU with [[PPU registers|memory mapped registers]] at $2006 and $2007.
The [[PPU]] addresses a 14-bit (16kB) address space, $0000-$3FFF, completely separate from the CPU's address bus. It is either directly accessed by the PPU itself, or via the CPU with [[PPU registers|memory mapped registers]] at $2006 and $2007.
 
The NES has 2kB of RAM dedicated to the PPU, normally mapped to the nametable address space from $2000-2FFF, but this can be rerouted through custom cartridge wiring.


{| class="tabular"
{| class="tabular"
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|-
|-
| $3F20-$3FFF  || $00E0 || Mirrors of $3F00-$3F1F || Internal to PPU
| $3F20-$3FFF  || $00E0 || Mirrors of $3F00-$3F1F || Internal to PPU
|}
In addition, the PPU internally contains 256 bytes of memory known as [[PPU OAM|Object Attribute Memory]] which determines how sprites are rendered. The CPU can manipulate this memory through [[PPU registers|memory mapped registers]] at [[OAMADDR]] ($2003), [[OAMDATA]] ($2004), and [[OAMDMA]] ($4014). OAM can be viewed as an array with 64 entries. Each entry has 4 bytes: the sprite Y coordinate, the sprite tile number, the sprite attribute, and the sprite X coordinate.
{| class="tabular"
! Address Low Nibble || Description
|-
| $00, $04, $08, $0C || Sprite Y coordinate
|-
| $01, $05, $09, $0D || Sprite tile #
|-
| $02, $06, $0A, $0E || Sprite attribute
|-
| $03, $07, $0B, $0F || Sprite X coordinate
|}
|}


== Hardware mapping ==
== Hardware mapping ==


The mappings above are the addresses from which the PPU uses to fetch data during rendering. The actual device that the PPU fetches pattern, name table and attribute table data from is configured by the cartridge.
The NES has 2kB of RAM dedicated to the PPU, usually mapped to the nametable address space from $2000-$2FFF, but this can be rerouted through custom cartridge wiring. The mappings above are the addresses from which the PPU uses to fetch data during rendering. The actual devices that the PPU fetches pattern, name table and attribute table data from is configured by the cartridge.


* $0000-1FFF is normally mapped by the cartridge to a [[CHR ROM vs. CHR RAM|CHR-ROM or CHR-RAM]], often with a bank switching mechanism.
* $0000-1FFF is normally mapped by the cartridge to a [[CHR ROM vs. CHR RAM|CHR-ROM or CHR-RAM]], often with a bank switching mechanism.
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* $3F00-3FFF is not configurable, always mapped to the internal palette control.
* $3F00-3FFF is not configurable, always mapped to the internal palette control.
== OAM ==
In addition, the PPU internally contains 256 bytes of memory known as [[PPU OAM|Object Attribute Memory]] which determines how sprites are rendered. The CPU can manipulate this memory through [[PPU registers|memory mapped registers]] at [[OAMADDR]] ($2003), [[OAMDATA]] ($2004), and [[OAMDMA]] ($4014). OAM can be viewed as an array with 64 entries. Each entry has 4 bytes: the sprite Y coordinate, the sprite tile number, the sprite attribute, and the sprite X coordinate.
{| class="tabular"
! Address Low Nibble || Description
|-
| $0, $4, $8, $C || Sprite Y coordinate
|-
| $1, $5, $9, $D || Sprite tile #
|-
| $2, $6, $A, $E || Sprite attribute
|-
| $3, $7, $B, $F || Sprite X coordinate
|}

Latest revision as of 22:43, 2 March 2024

PPU memory map

The PPU addresses a 14-bit (16kB) address space, $0000-$3FFF, completely separate from the CPU's address bus. It is either directly accessed by the PPU itself, or via the CPU with memory mapped registers at $2006 and $2007.

Address range Size Description Mapped by
$0000-$0FFF $1000 Pattern table 0 Cartridge
$1000-$1FFF $1000 Pattern table 1 Cartridge
$2000-$23BF $0400 Nametable 0 Cartridge
$2400-$27FF $0400 Nametable 1 Cartridge
$2800-$2BFF $0400 Nametable 2 Cartridge
$2C00-$2FFF $0400 Nametable 3 Cartridge
$3000-$3EFF $0F00 Unused Cartridge
$3F00-$3F1F $0020 Palette RAM indexes Internal to PPU
$3F20-$3FFF $00E0 Mirrors of $3F00-$3F1F Internal to PPU

Hardware mapping

The NES has 2kB of RAM dedicated to the PPU, usually mapped to the nametable address space from $2000-$2FFF, but this can be rerouted through custom cartridge wiring. The mappings above are the addresses from which the PPU uses to fetch data during rendering. The actual devices that the PPU fetches pattern, name table and attribute table data from is configured by the cartridge.

  • $0000-1FFF is normally mapped by the cartridge to a CHR-ROM or CHR-RAM, often with a bank switching mechanism.
  • $2000-2FFF is normally mapped to the 2kB NES internal VRAM, providing 2 nametables with a mirroring configuration controlled by the cartridge, but it can be partly or fully remapped to ROM or RAM on the cartridge, allowing up to 4 simultaneous nametables.
  • $3000-3EFF is usually a mirror of the 2kB region from $2000-2EFF. The PPU does not render from this address range, so this space has negligible utility.
  • $3F00-3FFF is not configurable, always mapped to the internal palette control.

OAM

In addition, the PPU internally contains 256 bytes of memory known as Object Attribute Memory which determines how sprites are rendered. The CPU can manipulate this memory through memory mapped registers at OAMADDR ($2003), OAMDATA ($2004), and OAMDMA ($4014). OAM can be viewed as an array with 64 entries. Each entry has 4 bytes: the sprite Y coordinate, the sprite tile number, the sprite attribute, and the sprite X coordinate.

Address Low Nibble Description
$0, $4, $8, $C Sprite Y coordinate
$1, $5, $9, $D Sprite tile #
$2, $6, $A, $E Sprite attribute
$3, $7, $B, $F Sprite X coordinate
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