PPU power up state

In March 2008, Blargg reverse-engineered the power-up/reset state and behavior of the NES PPU, NTSC version.

Initial Register Values

Register	At Power	After Reset
$2000	0x00 0000	0x00 0000
$2001	0000 0xx0	0000 0xx0
$2002	+0+x xxxx	U??x xxxx
$2003	$00	unchanged
$2005 lo/hi	cleared	cleared
$2005	$0000	$0000
$2006 lo/hi	cleared	cleared
$2006	$0000	unchanged
$2007	random	$00
odd frame	?	?
CHR RAM	pattern	unchanged
NT RAM	mostly $FF	unchanged
SPR RAM	pattern	pattern

? = unknown, x = irrelevant, + = often set, U = unchanged

• Writes to the following registers are ignored if earlier than ~29658 CPU clocks after reset: $2000, $2001, $2005, $2006. The other registers work immediately: $2002, $2003, $2004, $2007, $4014.
• If the NES is powered on after having been off for less than 20 seconds, register writes are ignored as if it were a reset, and register starting values differ: $2002 = $80 (VBL flag set), $2003 = $2F or $01, and $2006 = $0001 .
• The VBL flag ($2002 bit 7) is usually clear at power, and unchanged by reset. It is next set around 27384, then around 57165.
• These cycle values appear to correspond to numbers of scanlines. Specifically, 27384 is almost 241 * 341/3 (241 scanlines), 29658 is 9 clocks less than 261 scanlines, and 57165 is 29781 clocks (one normal frame) after 27384.
• Preliminary testing on a PAL NES shows that writes are ignored until ~33132 CPU clocks after power and reset, 9 clocks less than 311 scanlines. It is conjectured that the first VBL flag setting will be close to 241 * 341/3.2 cycles (241 PAL scanlines); further testing is needed to confirm this.
• It is known that after power and reset, it is as if the APU's $4017 were written 10 clocks before the first code starts executing. This delay is probably the same source of the 9 clock difference in the times for PPU writes being ignored. The cause is likely the reset sequence of the 2A03, when it reads the reset vector.