PPU registers: Difference between revisions

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__TOC__


{{:PPU_REGISTER_CONTROLLER}}
{{:PPU_REGISTER_CONTROLLER}}


{{:PPU_REGISTER_MASK}}
{{:PPU_REGISTER_MASK}}


{{:PPU_REGISTER_STATUS}}
{{:PPU_REGISTER_STATUS}}


{{:PPU_REGISTER_OAM_ADDRESS}}
{{:PPU_REGISTER_OAM_ADDRESS}}


{{:PPU_REGISTER_OAM_DATA}}
{{:PPU_REGISTER_OAM_DATA}}


{{:PPU_REGISTER_SCROLL}}
{{:PPU_REGISTER_SCROLL}}


{{:PPU_REGISTER_ADDRESS}}
{{:PPU_REGISTER_ADDRESS}}


{{:PPU_REGISTER_DATA}}
{{:PPU_REGISTER_DATA}}

Revision as of 07:46, 11 June 2009

The PPU exposes only eight memory-mapped registers to the CPU. These nominally sit at $2000 through $2007 in the CPU's address space, but because they're incompletely decoded, they're mirrored in every 8 bytes from $2008 through $3FFF, so a write to $3456 is the same as a write to $2006.

Note: The next paragraph explain details that should be more in the getting started reference?

Immediately after powerup, the PPU must wait at least one full frame before it is stable enough to operate normally. The first thing that should be done on startup is to write a zero byte to registers PPUCTRL and PPUMASK (to disable rendering and NMIs) and then wait for bit 7 of PPUSTATUS to be set twice. Some programs will wait for $2002 bit 7 to be set, initialize hardware other than the PPU (such as zeroing CPU RAM), and then wait for $2002 bit 7 to be set again.


PPU REGISTER CONTROLLER


PPU REGISTER MASK


PPU REGISTER STATUS


PPU REGISTER OAM ADDRESS


PPU REGISTER OAM DATA


PPU REGISTER SCROLL


PPU REGISTER ADDRESS


PPU REGISTER DATA