User contributions for Quietust
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15 June 2011
- 12:5812:58, 15 June 2011 diff hist −132 m Emulators duplicate
8 June 2011
- 16:4116:41, 8 June 2011 diff hist +16 m Talk:CPU power up state No edit summary
- 16:4016:40, 8 June 2011 diff hist +1,401 N Talk:CPU power up state using my previous trace of the reset line combined with the "regions" image overlay
- 02:1202:12, 8 June 2011 diff hist +63 m File:2a03 map.jpg there's now a layer image that highlights all of these regions
6 June 2011
- 03:0303:03, 6 June 2011 diff hist −2 m Talk:APU DMC No edit summary
- 03:0303:03, 6 June 2011 diff hist +336 Talk:APU DMC No edit summary
18 May 2011
- 20:4220:42, 18 May 2011 diff hist +106 m Talk:APU Sweep No edit summary
- 20:4120:41, 18 May 2011 diff hist +27 m Talk:APU Sweep the triangle channel is clocked by every M1 pulse, and the rest of the APU is clocked either by even M1 pulses or odd M1 pulses (with a vast majority being even)
- 17:1517:15, 18 May 2011 diff hist +500 Talk:APU Sweep No edit summary
- 03:4903:49, 18 May 2011 diff hist +399 Talk:APU Sweep No edit summary
16 May 2011
- 02:2202:22, 16 May 2011 diff hist −274 File:2a03 map.jpg created a chip images index page on my site
14 May 2011
- 17:1617:16, 14 May 2011 diff hist +398 Talk:APU Sweep food for thought and/or research
- 16:5616:56, 14 May 2011 diff hist +14 APU Sweep clarify
- 16:4616:46, 14 May 2011 diff hist +104 APU Sweep the problem isn't in pulse 2, but in pulse 1 - pulse 2 adds the two's complement during subtraction (as it should), but pulse 1 adds the ONE'S complement due to its carry input being hardwired
- 16:3716:37, 14 May 2011 diff hist +131 APU Pulse The duty cycle counter actually counts downward (since it's triggered by frequency counter underflow), but it's initialized to 000 rather than 111, which explains the waveform sequences
11 May 2011
- 03:1803:18, 11 May 2011 diff hist −10 File:Apu address.jpg it also overrides the noise channel's LFSR output and appears to also stop the triangle channel from being clocked; I don't know what it does to DPCM, but it's probably something similar current
- 03:0303:03, 11 May 2011 diff hist +12 File:Apu address.jpg setting $401A.7 prevents the square channels from outputting 0000, whether from the duty cycle generator, the sweep unit, or the length counter; the effect on triangle/noise/PCM is still unclear
10 May 2011
- 15:4615:46, 10 May 2011 diff hist +700 Talk:APU Frame Counter No edit summary
- 00:4500:45, 10 May 2011 diff hist +462 N Talk:APU Sweep an amusing thing I noticed a while ago - the actual reason why the sweep units in the 2 square channels behave slightly differently
9 May 2011
- 15:3415:34, 9 May 2011 diff hist +9 CPU pinout STR/E44/E45 are better known as OUT0/OUT1/OUT2; also, strobe is OUT, not D0
- 15:2115:21, 9 May 2011 diff hist +720 Talk:CPU pinout located the main side effect of pulling pin 30 high - all readable registers in $4000-$401F go internal, so the joypads stop working
7 May 2011
- 20:3320:33, 7 May 2011 diff hist −123 m Talk:CPU pinout traced enough of it to determine this - if both /RESET and pin 30 are low, then the output drivers for M2 will be disabled and the pin will float
- 19:4519:45, 7 May 2011 diff hist +634 m Talk:CPU pinout figured out the part that goes to M2 - it's merged with /RESET
2 May 2011
- 15:4015:40, 2 May 2011 diff hist +69 m User:Quietust not yet tested, though
- 15:3815:38, 2 May 2011 diff hist −65 m Nintendulator does not use inline assembly anymore
- 15:3815:38, 2 May 2011 diff hist +372 User:Quietust put RP2A03G die analysis findings somewhere convenient
29 April 2011
- 16:4916:49, 29 April 2011 diff hist +37 Talk:CPU pinout No edit summary
- 16:3216:32, 29 April 2011 diff hist +463 File:2a03 map.jpg fully traced every single layer of the RP2A03G - these have also been submitted to visual6502.org for potential simulation
17 April 2011
- 17:2617:26, 17 April 2011 diff hist +781 N Talk:Sunsoft FME-7 ...
2 April 2011
- 01:5001:50, 2 April 2011 diff hist +119 m File:2a03 map.jpg No edit summary
- 01:4801:48, 2 April 2011 diff hist +245 N File:2a03 map.jpg A rough diagram of where everything is physically located on the RP2A03G. The clock divider, not highlighted, is at the far right. The purpose of the large section at the upper right is not known - none of it has any connection to anything else.
30 March 2011
- 15:5215:52, 30 March 2011 diff hist 0 m Talk:CPU pinout No edit summary
- 15:5115:51, 30 March 2011 diff hist +82 m Talk:CPU pinout my mistake - they're all enhancement mode (VCC->gate = source and drain connected), but ones with "thick" gates are effectively resistors when off (where "thicker" == lower resistance)
20 March 2011
- 00:1900:19, 20 March 2011 diff hist +42 Talk:CPU pinout getting better at reading these images, but not quite good enough...
1 March 2011
- 19:4719:47, 1 March 2011 diff hist +262 m Talk:CPU pinout No edit summary
28 February 2011
- 03:0503:05, 28 February 2011 diff hist +148 m Talk:INES Mapper 068 found it
27 February 2011
- 21:5921:59, 27 February 2011 diff hist +452 N Talk:INES Mapper 068 ...what about 1-screen mirroring?
- 16:5316:53, 27 February 2011 diff hist +58 INES Mapper 068 clarify nametable registers - $C000 overrides the lower nametable and $D000 overrides the upper nametable, then mirroring gets done accordingly
- 04:1504:15, 27 February 2011 diff hist +180 N Talk:CPU pinout I think I've figured it out...
- 04:0204:02, 27 February 2011 diff hist +48 File:Apu address.jpg traced out all of the registers, and I've located what W$401A is connected to - triangle wave position (D0-D4) and something I don't recognize (D7)
12 February 2011
- 03:3703:37, 12 February 2011 diff hist 0 m Cartridge connector *ahem*
4 February 2011
- 14:0414:04, 4 February 2011 diff hist +15 m Programming with unofficial opcodes →Combined operations: s/N/Z/
- 13:5613:56, 4 February 2011 diff hist −67 Programming with unofficial opcodes it most definitely does set N - blargg's instr_test-v3 fails if it doesn't
2 February 2011
- 16:1116:11, 2 February 2011 diff hist +194 Myths →Old tutorials: people need to know WHY the gbaguy tutorial is wrong - explicitly point out some of its mistakes
- 16:0616:06, 2 February 2011 diff hist +52 Myths →Mappers: the VRC6 uses 16K/8K/8K banking, and the MMC5 happens to support this mode
31 January 2011
- 17:4417:44, 31 January 2011 diff hist +133 m INES Mapper 119 →Variants
- 17:4217:42, 31 January 2011 diff hist +84 m INES Mapper 192 better comparison
24 January 2011
- 15:3115:31, 24 January 2011 diff hist +122 m File:Apu address.jpg anybody capable of interpreting these images is welcome to figure out how to enable these extra registers...
- 15:2615:26, 24 January 2011 diff hist +509 N File:Apu address.jpg The NES APU's address decoder, generating enables for all reads/writes within $4000-$401F. Of very special note are the 4 signals at the very top for readable registers at $4018 (pulse 0 output on D0-D3 and pulse 1 output on D4-D7), $4019 (triangle outpu
- 00:2900:29, 24 January 2011 diff hist +13 m Talk:APU DMC this too
