User contributions for Quietust
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15 June 2011
- 12:5812:58, 15 June 2011 diff hist −132 m Emulators duplicate
8 June 2011
- 16:4116:41, 8 June 2011 diff hist +16 m Talk:CPU power up state No edit summary
- 16:4016:40, 8 June 2011 diff hist +1,401 N Talk:CPU power up state using my previous trace of the reset line combined with the "regions" image overlay
- 02:1202:12, 8 June 2011 diff hist +63 m File:2a03 map.jpg there's now a layer image that highlights all of these regions
6 June 2011
- 03:0303:03, 6 June 2011 diff hist −2 m Talk:APU DMC No edit summary
- 03:0303:03, 6 June 2011 diff hist +336 Talk:APU DMC No edit summary
18 May 2011
- 20:4220:42, 18 May 2011 diff hist +106 m Talk:APU Sweep No edit summary
- 20:4120:41, 18 May 2011 diff hist +27 m Talk:APU Sweep the triangle channel is clocked by every M1 pulse, and the rest of the APU is clocked either by even M1 pulses or odd M1 pulses (with a vast majority being even)
- 17:1517:15, 18 May 2011 diff hist +500 Talk:APU Sweep No edit summary
- 03:4903:49, 18 May 2011 diff hist +399 Talk:APU Sweep No edit summary
16 May 2011
- 02:2202:22, 16 May 2011 diff hist −274 File:2a03 map.jpg created a chip images index page on my site
14 May 2011
- 17:1617:16, 14 May 2011 diff hist +398 Talk:APU Sweep food for thought and/or research
- 16:5616:56, 14 May 2011 diff hist +14 APU Sweep clarify
- 16:4616:46, 14 May 2011 diff hist +104 APU Sweep the problem isn't in pulse 2, but in pulse 1 - pulse 2 adds the two's complement during subtraction (as it should), but pulse 1 adds the ONE'S complement due to its carry input being hardwired
- 16:3716:37, 14 May 2011 diff hist +131 APU Pulse The duty cycle counter actually counts downward (since it's triggered by frequency counter underflow), but it's initialized to 000 rather than 111, which explains the waveform sequences
11 May 2011
- 03:1803:18, 11 May 2011 diff hist −10 File:Apu address.jpg it also overrides the noise channel's LFSR output and appears to also stop the triangle channel from being clocked; I don't know what it does to DPCM, but it's probably something similar current
- 03:0303:03, 11 May 2011 diff hist +12 File:Apu address.jpg setting $401A.7 prevents the square channels from outputting 0000, whether from the duty cycle generator, the sweep unit, or the length counter; the effect on triangle/noise/PCM is still unclear
10 May 2011
- 15:4615:46, 10 May 2011 diff hist +700 Talk:APU Frame Counter No edit summary
- 00:4500:45, 10 May 2011 diff hist +462 N Talk:APU Sweep an amusing thing I noticed a while ago - the actual reason why the sweep units in the 2 square channels behave slightly differently
9 May 2011
- 15:3415:34, 9 May 2011 diff hist +9 CPU pinout STR/E44/E45 are better known as OUT0/OUT1/OUT2; also, strobe is OUT, not D0