Taito X1-017: Difference between revisions

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(Created page with "Category:iNES Mappers Here are Disch's original notes: ======================== = Mapper 082 = ======================== Example Games: ---------…")
 
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[[Category:iNES Mappers]]
[[Category:iNES Mappers|082]][[Category:in NesCartDB|082]]
  Here are Disch's original notes: 
[[iNES Mapper 082]] represents boards using Taito's X1-017 mapper IC, which provides something a little more sophisticated than [[MMC3]]. It loses the indirect addressing, adds a 3rd 8 KiB ROM slice, and has 5 KiB of battery-backed RAM.
  ========================
 
  =  Mapper 082          =
The cartridge connector's /IRQ line ''is'' connected to the mapper IC, but it is not known how to trigger one.
  ========================
 
 
== Overview ==
 
* PRG ROM size: 256 KiB (maybe 512 KiB?)
  Example Games:
* PRG ROM bank size: 8 KiB
  --------------------------
* PRG RAM: Yes, internal, battery backed.
  SD Keiji - Blader
* CHR capacity: 256 KiB ROM
  Kyuukyoku Harikiri Stadium
* CHR bank size: 1 KiB and 2 KiB
 
* Nametable [[mirroring]]: Controlled by mapper
 
* Subject to [[bus conflict]]s: no
  Notes:
 
  ---------------------------
== Banks ==
  Regs appear at $7EFx, I'm unsure whether or not PRG-RAM can exist at $6000-7FFF
* CPU $6000-$67FF: 2 KiB PRG RAM bank
 
* CPU $7000-$6FFF: 2 KiB PRG RAM bank
 
* CPU $7000-$73FF: 1 KiB PRG RAM bank
  Registers:
<!-- what's between $7400 and $7EEF ? -->
  ---------------------------
* CPU $7EF0-$7EFF: Mapper registers
 
* CPU $8000-$9FFF: 8 KB switchable PRG ROM bank
    $7EF0-7EF5: CHR Regs
* CPU $A000-$BFFF: 8 KB switchable PRG ROM bank
 
* CPU $C000-$DFFF: 8 KB switchable PRG ROM bank
    $7EF6: [.... ..CM]  CHR Mode/Mirroring
* CPU $E000-$FFFF: 8 KB PRG ROM bank, fixed to the last bank
      C = CHR Mode select
* PPU $0000-$07FF (or $1000-$17FF): 2 KB switchable CHR bank
      M = Mirroring:
* PPU $0800-$0FFF (or $1800-$1FFF): 2 KB switchable CHR bank
        0 = Horz
* PPU $1000-$13FF (or $0000-$03FF): 1 KB switchable CHR bank
        1 = Vert
* PPU $1400-$17FF (or $0400-$07FF): 1 KB switchable CHR bank
 
* PPU $1800-$1BFF (or $0800-$0BFF): 1 KB switchable CHR bank
    $7EFA: [PPPP PP..] PRG Reg 0 (8k @ $8000)
* PPU $1C00-$1FFF (or $0C00-$0FFF): 1 KB switchable CHR bank
    $7EFB: [PPPP PP..] PRG Reg 1 (8k @ $A000)
 
    $7EFC: [PPPP PP..] PRG Reg 2 (8k @ $C000)
== Registers ==
 
=== CHR Select 0 ($7EF0) ===
 
  7  bit 0
  CHR Setup:
  CCCC CCC.
  ---------------------------
|||| |||
 
  ++++-+++-- Select 2 KiB CHR ROM at PPU $0000 or $1000
                  $0000  $0400  $0800  $0C00  $1000  $1400   $1800  $1C00
 
                +---------------+---------------+-------+-------+-------+-------+
=== CHR Select 1 ($7EF1) ===
  CHR Mode 0:  |   <$7EF0>    |   <$7EF1>    | $7EF2 | $7EF3 | $7EF4 | $7EF5 |
7  bit  0
                +---------------+---------------+---------------+---------------+
  CCCC CCC.
  CHR Mode 1:  | $7EF2 | $7EF3 | $7EF4 | $7EF5 |   <$7EF0>    |   <$7EF1>    |
|||| |||
                +-------+-------+-------+-------+---------------+---------------+
  ++++-+++-- Select 2 KiB CHR ROM at PPU $0800 or $1800
 
 
 
=== CHR Select 2 ($7EF2) ===
  PRG Setup:
7  bit  0
  ---------------------------
CCCC CCCC
 
|||| ||||
        $8000  $A000  $C000  $E000  
++++-++++- Select 1 KiB CHR ROM at PPU $1000 or $0000
      +-------+-------+-------+-------+
 
      | $7EFA | $7EFB | $7EFC | { -1} |
=== CHR Select 3 ($7EF3) ===
      +-------+-------+-------+-------+
7  bit  0
 
CCCC CCCC
  Note:  remember that the low 2 bits are not used (right-shift written values by 2)
|||| ||||
++++-++++- Select 1 KiB CHR ROM at PPU $1400 or $0400
 
=== CHR Select 4 ($7EF4) ===
7  bit  0
CCCC CCCC
|||| ||||
++++-++++- Select 1 KiB CHR ROM at PPU $1800 or $0800
 
=== CHR Select 5 ($7EF5) ===
7  bit  0
CCCC CCCC
|||| ||||
++++-++++- Select 1 KiB CHR ROM at PPU $1C00 or $0C00
 
=== CHR Mode / Mirroring Control ($7EF6) ===
7  bit  0
.... ..CM
        ||
        |+- Mirroring (0:Horizontal, 1:Vertical)
        +-- CHR A12 inversion (0: two 2 KB banks at $0000-$0FFF,
                                  four 1 KB banks at $1000-$1FFF;
                              1: two 2 KB banks at $1000-$1FFF,
                                  four 1 KB banks at $0000-$0FFF)
 
=== PRG RAM enable 0 ($7EF7) ===
7  bit  0
XXXX XXXX
|||| ||||
++++-++++- Write $CA to enable RAM from $6000 to $67FF, write anything else to disable
 
=== PRG RAM enable 1 ($7EF8) ===
7  bit  0
XXXX XXXX
|||| ||||
++++-++++- Write $69 to enable RAM from $6000 to $67FF, write anything else to disable
 
=== PRG RAM enable 2 ($7EF9) ===
7  bit  0
  XXXX XXXX
|||| ||||
++++-++++- Write $84 to enable RAM from $6000 to $67FF, write anything else to disable
 
=== PRG Select 0 ($7EFA) ===
7  bit  0
PPPP PP..
|||| ||
++++-++--- Select 8 KiB PRG ROM at $8000
Note:  remember that the low 2 bits are not used (right-shift written values by 2)
 
=== PRG Select 1 ($7EFB) ===
7  bit  0
PPPP PP..
|||| ||
++++-++--- Select 8 KiB PRG ROM at $A000
 
=== PRG Select 2 ($7EFC) ===
7  bit  0
PPPP PP..
|||| ||
++++-++--- Select 8 KiB PRG ROM at $C000
 
== Example Games ==
* SD Keiji - Blader
* Kyuukyoku Harikiri Stadium
 
== References ==
* BootGod mentions the RAM protect registers: http://nesdev.parodius.com/bbs/viewtopic.php?p=30165

Revision as of 00:33, 3 August 2012

iNES Mapper 082 represents boards using Taito's X1-017 mapper IC, which provides something a little more sophisticated than MMC3. It loses the indirect addressing, adds a 3rd 8 KiB ROM slice, and has 5 KiB of battery-backed RAM.

The cartridge connector's /IRQ line is connected to the mapper IC, but it is not known how to trigger one.

Overview

  • PRG ROM size: 256 KiB (maybe 512 KiB?)
  • PRG ROM bank size: 8 KiB
  • PRG RAM: Yes, internal, battery backed.
  • CHR capacity: 256 KiB ROM
  • CHR bank size: 1 KiB and 2 KiB
  • Nametable mirroring: Controlled by mapper
  • Subject to bus conflicts: no

Banks

  • CPU $6000-$67FF: 2 KiB PRG RAM bank
  • CPU $7000-$6FFF: 2 KiB PRG RAM bank
  • CPU $7000-$73FF: 1 KiB PRG RAM bank
  • CPU $7EF0-$7EFF: Mapper registers
  • CPU $8000-$9FFF: 8 KB switchable PRG ROM bank
  • CPU $A000-$BFFF: 8 KB switchable PRG ROM bank
  • CPU $C000-$DFFF: 8 KB switchable PRG ROM bank
  • CPU $E000-$FFFF: 8 KB PRG ROM bank, fixed to the last bank
  • PPU $0000-$07FF (or $1000-$17FF): 2 KB switchable CHR bank
  • PPU $0800-$0FFF (or $1800-$1FFF): 2 KB switchable CHR bank
  • PPU $1000-$13FF (or $0000-$03FF): 1 KB switchable CHR bank
  • PPU $1400-$17FF (or $0400-$07FF): 1 KB switchable CHR bank
  • PPU $1800-$1BFF (or $0800-$0BFF): 1 KB switchable CHR bank
  • PPU $1C00-$1FFF (or $0C00-$0FFF): 1 KB switchable CHR bank

Registers

CHR Select 0 ($7EF0)

7  bit  0
CCCC CCC.
|||| |||
++++-+++-- Select 2 KiB CHR ROM at PPU $0000 or $1000

CHR Select 1 ($7EF1)

7  bit  0
CCCC CCC.
|||| |||
++++-+++-- Select 2 KiB CHR ROM at PPU $0800 or $1800

CHR Select 2 ($7EF2)

7  bit  0
CCCC CCCC
|||| ||||
++++-++++- Select 1 KiB CHR ROM at PPU $1000 or $0000

CHR Select 3 ($7EF3)

7  bit  0
CCCC CCCC
|||| ||||
++++-++++- Select 1 KiB CHR ROM at PPU $1400 or $0400

CHR Select 4 ($7EF4)

7  bit  0
CCCC CCCC
|||| ||||
++++-++++- Select 1 KiB CHR ROM at PPU $1800 or $0800

CHR Select 5 ($7EF5)

7  bit  0
CCCC CCCC
|||| ||||
++++-++++- Select 1 KiB CHR ROM at PPU $1C00 or $0C00

CHR Mode / Mirroring Control ($7EF6)

7  bit  0
.... ..CM
       ||
       |+- Mirroring (0:Horizontal, 1:Vertical)
       +-- CHR A12 inversion (0: two 2 KB banks at $0000-$0FFF,
                                 four 1 KB banks at $1000-$1FFF;
                              1: two 2 KB banks at $1000-$1FFF,
                                 four 1 KB banks at $0000-$0FFF)

PRG RAM enable 0 ($7EF7)

7  bit  0
XXXX XXXX
|||| ||||
++++-++++- Write $CA to enable RAM from $6000 to $67FF, write anything else to disable

PRG RAM enable 1 ($7EF8)

7  bit  0
XXXX XXXX
|||| ||||
++++-++++- Write $69 to enable RAM from $6000 to $67FF, write anything else to disable

PRG RAM enable 2 ($7EF9)

7  bit  0
XXXX XXXX
|||| ||||
++++-++++- Write $84 to enable RAM from $6000 to $67FF, write anything else to disable

PRG Select 0 ($7EFA)

7  bit  0
PPPP PP..
|||| ||
++++-++--- Select 8 KiB PRG ROM at $8000

Note: remember that the low 2 bits are not used (right-shift written values by 2)

PRG Select 1 ($7EFB)

7  bit  0
PPPP PP..
|||| ||
++++-++--- Select 8 KiB PRG ROM at $A000

PRG Select 2 ($7EFC)

7  bit  0
PPPP PP..
|||| ||
++++-++--- Select 8 KiB PRG ROM at $C000

Example Games

  • SD Keiji - Blader
  • Kyuukyoku Harikiri Stadium

References

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