Talk:APU DMC: Difference between revisions
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I suspect there's no "address increment", but ''another'' shift register. Just pay attention to the address wrap - if we had a counter, it would wrap to zero, but instead, it wraps to $8000, like ($10000 >> 1). | I suspect there's no "address increment", but ''another'' shift register. Just pay attention to the address wrap - if we had a counter, it would wrap to zero, but instead, it wraps to $8000, like ($10000 >> 1). | ||
--[[User:Zepper|Zepper]] 01:49, 6 June 2011 (UTC) | --[[User:Zepper|Zepper]] 01:49, 6 June 2011 (UTC) | ||
:The generated addresses are linear, and I don't think a shift register can do that. So I'm conjecturing an up-counter here. --[[User:Tepples|Tepples]] 02:30, 6 June 2011 (UTC) | |||
Revision as of 02:30, 6 June 2011
Similarly to the noise channel, the DPCM channel's frequency counter on the die is a 9-bit linear feedback shift register (with taps at the 5th and 9th bits); when I take the counter values from the on-die ROM and run the LFSR until the result is '100000000', the cycle counts (for NTSC) match once multiplied by 2. --Quietust 05:00, 23 January 2011 (UTC)
I suspect there's no "address increment", but another shift register. Just pay attention to the address wrap - if we had a counter, it would wrap to zero, but instead, it wraps to $8000, like ($10000 >> 1). --Zepper 01:49, 6 June 2011 (UTC)
- The generated addresses are linear, and I don't think a shift register can do that. So I'm conjecturing an up-counter here. --Tepples 02:30, 6 June 2011 (UTC)
