Talk:Clock rate

Divider

Ok, ok. I went to the visual2A03, saw that Quietust had implemented a "microstep" function which drives the 2A03's clock input (instead of the inside 6502's φ0 input), and so tested this. In the 2A03, the input clock is implemented using a Johnson counter, which intrinsically divides by an even number. They couldn't use the same design to divide by 15, so they instead divided by 16.

Interestingly, there is even two more unused bits on this divider (off the bottom), so maybe by the time they made the 2A03G's die they had unified the 2A07 and 2A03 designs sufficiently to just be a "move this tap from here to here".

Dividing by 15 would have required an entire different design, and I suspect that the smallest ÷15 circuit (4 bit binary counter plus 4-input AND gate) would have taken more silicon die space than the 8-stage Johnson counter they used. —Lidnariq 00:05, 4 September 2012 (MDT)

The CIC uses a polynomial counter for the program counter to save die space. How hard would it have been to use a 4-bit linear feedback shift register to divide by 15? I guess there would have to be some post-decoding of the LFSR's state to produce a binary clock signal, and that might have taken a lot of space too. --Tepples 08:13, 4 September 2012 (MDT)

I don't know if it's a requirement of the output, but a johnson counter very conveniently has each bit output equal time high and low, doesn't it? If you an effective 15x divide with equal time high/low, would you actually need a 30x divider that is clocked twice as fast? - Rainwarrior 12:20, 4 September 2012 (MDT)