Talk:J.Y. Company ASIC

PPU read IRQ mode

I don't see why the PPU read mode of the interval timer should be labeled "wtf". Wouldn't an IRQ mode based on PPU reads just clock 170 times per scanline? It'd be sort of like CPU mode, except not dependent on the CPU to PPU clock ratio. And it'd be unaffected by "borrowing" 8x16 sprites from the other pattern table, which trips up PA12-rise PITs such as MMC3's. With the /256 prescaler, it would appear fairly straightforward to work with: as the last thing in vblank, load 170/256 (very close to two-thirds) times the number of scanlines to wait. Apart from "CPU writes" and "funky mode", I see nothing particularly strange about 90's PIT. Or is there something harsh that I'm missing? --Tepples (talk) 23:04, 10 May 2014 (MDT)

When Disch wrote these, he had Strong Opinions about anything that wasn't MMC3-shaped. See also his original writeup of Bandai LZ93D50 EEPROM traffic[1]. —Lidnariq (talk) 00:19, 11 May 2014 (MDT)