Talk:Mirroring: Difference between revisions
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Using a single and-or-invert gate, or three NAND or NOR gates, along with two bits from a latch gets you controllable 1/H/V/L mirroring. This is roughly what mapper 243 does. —[[User:Lidnariq|Lidnariq]] ([[User talk:Lidnariq|talk]]) 00:32, 4 May 2013 (MDT) | Using a single and-or-invert gate, or three NAND or NOR gates, along with two bits from a latch gets you controllable 1/H/V/L mirroring. This is roughly what mapper 243 does. —[[User:Lidnariq|Lidnariq]] ([[User talk:Lidnariq|talk]]) 00:32, 4 May 2013 (MDT) | ||
Revision as of 17:29, 7 October 2014
PAxx vs. PPU Axx vs. CHR Axx
These edits by infiniteneslives confuse me a bit. I've seen "CHR A10" and "CHR A11" used for the lines going to the CHR ROM. In ASIC mappers, these tend not to match PPU A10 (PA10 for short) and PPU A11 (PA11). --Tepples (talk) 12:04, 23 February 2013 (MST)
"L" mirroring
Using a single and-or-invert gate, or three NAND or NOR gates, along with two bits from a latch gets you controllable 1/H/V/L mirroring. This is roughly what mapper 243 does. —Lidnariq (talk) 00:32, 4 May 2013 (MDT)
