UNROM 512

UNROM 512 is a discrete-logic board made by RetroUSB as an extension of UNROM with up to 512k of PRG ROM, bankable CHR RAM, an option for mapper-controlled single-screen mirroring, as well as a self-flashable configuration for rewriting PRG.

The iNES format assigns iNES Mapper 030 to UNROM 512.

The UNIF names for this board are UNROM-512-8, UNRROM-512-16 and UNROM-512-32, depending on how much CHR RAM is present.

Games that use this board include:

• Study Hall
• Battle Kid 2: Mountain of Torment

Overview

• PRG ROM size: 512 KB
• PRG ROM bank size: 16 KB
• PRG RAM: None
• CHR capacity: Up to 32 KB RAM
• CHR bank size: 8 KB
• Nametable mirroring: Solder pads select vertical, horizontal, or mapper-controlled one-screen
• Subject to bus conflicts: Yes, in the non-flashable configuration

Board

The example board in question is marked as follows: "Sealie Computing", "12/29/2011 revA", "UNROM 512". The backside of the board was mislabeled with "ReproPak MMC3".

The board includes 4x banks worth of full 8KB CHR ram (Configurable by jumpers) and 32x 16KB PRG banks.

The board can be wired in a not flashable, or self flashable configuration. Mirroring can be selected between Horizontal, Vertical, and Mapper controlled One Screen.

Bus conflicts are only present on the non-flashable configuration of the board.

Some images of the board:

• Study Hall PCB Front
• Battle Kid 2 PCB Front
• PCB Back

When board is not flashable:

  Registers:
  ---------------------------
  
  Range,Mask:   $8000-FFFF, $8000
  
    $8000:  [MCCP PPPP]
      M = One screen Mirroring select
      C = CHR RAM bank
      P = PRG ROM bank
  
  PRG Setup:
  ---------------------------
       $8000   $A000   $C000   $E000  
      +-------------------------------+
      |     $8000     |     { -1}     |
      +---------------+---------------+
  
  CHR Setup:
  ---------------------------
        $0000   $1000   
      +-------+-------+
      |     $0000     |
      +-------+-------+

When board is self flashable:

  Registers:
  ---------------------------
  
  Range,Mask:   $8000-BFFF, $8000
                $C000-FFFF, $C000
  
    $8000:  [.... ....]
      Write a sequence of bytes here for writing to the flash. The sequence is as follows 

(This code must exist in wram):
        Erase 4KB Flash Sector:
        $C000:$01, $9555:$AA
        $C000:$00, $AAAA:$55
        $C000:$01, $9555:$80
        $C000:$01, $9555:$AA
        $C000:$00, $AAAA:$55
        $C000:BANK, ADDR:$30 (Where BANK is $00-1F, ADDR is $8000,$9000,$A000,$B000)
        Read the written location twice until you get $FF twice.

        Write a byte:
        $C000:$01, $9555:$AA
        $C000:$00, $AAAA:$55
        $C000:$01, $9555:$A0
        $C000:BANK, ADDR:DATA (Where BANK is $00-1F, ADDR is $8000-$BFFF, DATA is $00-$FF)
        Read the written location twice until you get DATA twice.
  
    $C000:  [MCCP PPPP]
      M = One screen Mirroring select
      C = CHR RAM bank
      P = PRG ROM bank
  
  PRG Setup:
  ---------------------------
       $8000   $A000   $C000   $E000  
      +-------------------------------+
      |     $8000     |     { -1}     |
      +---------------+---------------+
  
  CHR Setup:
  ---------------------------
        $0000   $1000   
      +-------+-------+
      |     $8000     |
      +-------+-------+

Here's a schematic of the board:

             ____
A14 ---------\    \
              )    >--- ROM A14
377 Q0 ------/____/

             ____
A14 ---------\    \
              )    >--- ROM A15
377 Q1 ------/____/

             ____
A14 ---------\    \
              )    >--- ROM A16
377 Q2 ------/____/

             ____
A14 ---------\    \
              )    >--- ROM A17
377 Q3 ------/____/

             ____
A14 ---------\    \
              )    >--- ROM A18
377 Q4 ------/____/

16/32KB CHRRAM
377 Q5 --[]--+-- CHRRAM A13
             |
VCC -----[]--+
8KB CHRRAM

8/16KB CHRRAM
VCC -----[]--+
             |
377 Q6 --[]--+-- CHRRAM A14
32KB CHRRAM

ONE
377 Q7 --[]--+
             |
VERT         |
PPU A10 -[]--+-- CIRAM_A10
             |
HORIZ        |
PPU A11 -[]--+

FLASHLOCKED3
R/W ------[]-+
             |
FLASHABLE    |
GND ------[]-+-- 377_/CE

FLASHLOCKED1
VCC ------[]-------+
          ½74LS139 |
          .------. |
CPUA14----|A   Y0|-+- PRGROM_/WE
R/W ------|B   Y1|-+- 377_CLK
          |    Y2| |
/ROMSEL-+-|G   Y3| |
      |   '------' |
      |            |
      +---[]-------+
       FLASHLOCKED2

FLASHLOCKED4
GND ------[]-----+
        ½74LS139 |
        .------. |
R/W ----|A   Y0| |
GND ----|B   Y1|-+- PRGROM_/OE
        |    Y2|
/ROMSEL-|G   Y3|
        '------'

The board is wired in one of the following configurations:

Not Flashable:

• All 4 Flash Locked jumpers are soldered.
• Flashable jumper is not soldered.
• 74*139 is not mounted.
• This configuration is subject to bus conflicts

Flashable:

• All 4 Flash Locked jumpers are not soldered.
• Flashable jumper is soldered.
• 74*139 is mounted.
• This configuration is not subject to bus conflicts

The Self-flashable configuration should be implemented according to the SST39F040's datasheet.

Mapper

NES 2.0 may specify the CHR RAM size from 8 to 32 KB, but the default for iNES should to use 32 KB.

If the Battery flag is set, which indicates the mapper is flashable, then no bus conflicts should be emulated. On the other hand, bus conflicts should be emulated if the battery flag is cleared.

Mapper controlled one-screen mirroring is only emulated if the Four-Screen mirroring flag is set, otherwise, it is hard-locked on either horizontal or vertical mirroring.

Mapper 30 is currently only using sub mapper 0. The other sub mappers are reserved for future use.

Supported in FCEUX as of r3071