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| [[Category:ASIC mappers]] | | #REDIRECT [[VRC2 and VRC4]] |
| The Konami VRC2 is an [[:Category:ASIC mappers|ASIC]] [[MMC|mapper]].
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| __TOC__
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| == Overview ==
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| * PRG ROM bank size: 8 KB at $8000, and $A000
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| * PRG RAM: Unknown (none?)
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| * CHR bank size: 1 KB
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| * Nametable [[mirroring]]: Controlled by mapper
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| * Subject to [[bus conflict]]s: No
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| The Konami VRC2 is almost identical to the [[VRC4|VRC4]], but a bit more limited.
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| == Revisions ==
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| This mapper had two known revisions: VRC2a and VRC2b. Both revisions uses Address lines A0, A1, and A12-A15 for registers, however VRC2a has A0 and A1 "backwards" from the norm. Address $x001 on VRC2b would be $x002 on VRC2a, and $x002 on VRC2b would be $x001 on VRC2a.
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| Additionally, VRC2a has 7-bit wide CHR registers, whereas VRC2b has 8-bit wide CHR registers.
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| This page lists registers as they are in the VRC2b variant. For VRC2a registers, reverse A0 and A1 lines.
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| == Registers ==
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| === PRG Select 0 ($8000, $8001, $8002, $8003) ===
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| 7 bit 0
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| ---------
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| .... PPPP
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| ||||
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| ++++- Select 8 KB PRG bank at $8000
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| === PRG Select 1 ($A000, $A001, $A002, $A003) ===
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| 7 bit 0
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| ---------
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| .... PPPP
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| ||||
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| ++++- Select 8 KB PRG bank at $A000
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| === Mirroring Control ($9000, $9001, $9002, $9003) ===
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| 7 bit 0
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| ---------
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| .... ..MM
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| ++- [[Mirroring]] (0: vertical; 1: horizontal;
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| 2: one-screen, lower bank; 3: one-screen, upper bank;)
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| === CHR Select 0 ($B000 + $B001) ===
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| $B000 $B001
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| 7 bit 0 7 bit 0
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| --------- ---------
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| .... LLLL .... HHHH
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| |||| ||||
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| |||| ++++- High 4-bits of 1 KB CHR bank at PPU $0000
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| ++++-------------- Low 4-bits
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| Note: On VRC2a, the low bit is ignored (right shift value by 1)
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| === CHR Select 1 ($B002 + $B003) ===
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| $B002 $B003
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| 7 bit 0 7 bit 0
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| --------- ---------
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| .... LLLL .... HHHH
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| |||| ||||
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| |||| ++++- High 4-bits of 1 KB CHR bank at PPU $0400
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| ++++-------------- Low 4-bits
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| Note: On VRC2a, the low bit is ignored (right shift value by 1)
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| === CHR Select 2 ($C000 + $C001) ===
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| $C000 $C001
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| 7 bit 0 7 bit 0
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| --------- ---------
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| .... LLLL .... HHHH
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| |||| ||||
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| |||| ++++- High 4-bits of 1 KB CHR bank at PPU $0800
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| ++++-------------- Low 4-bits
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| Note: On VRC2a, the low bit is ignored (right shift value by 1)
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| === CHR Select 3 ($C002 + $C003) ===
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| $C002 $C003
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| 7 bit 0 7 bit 0
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| --------- ---------
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| .... LLLL .... HHHH
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| |||| ||||
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| |||| ++++- High 4-bits of 1 KB CHR bank at PPU $0C00
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| ++++-------------- Low 4-bits
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| Note: On VRC2a, the low bit is ignored (right shift value by 1)
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| === CHR Select 4 ($D000 + $D001) ===
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| $D000 $D001
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| 7 bit 0 7 bit 0
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| --------- ---------
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| .... LLLL .... HHHH
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| |||| ||||
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| |||| ++++- High 4-bits of 1 KB CHR bank at PPU $1000
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| ++++-------------- Low 4-bits
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| Note: On VRC2a, the low bit is ignored (right shift value by 1)
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| === CHR Select 5 ($D002 + $D003) ===
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| $D002 $D003
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| 7 bit 0 7 bit 0
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| --------- ---------
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| .... LLLL .... HHHH
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| |||| ||||
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| |||| ++++- High 4-bits of 1 KB CHR bank at PPU $1400
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| ++++-------------- Low 4-bits
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| Note: On VRC2a, the low bit is ignored (right shift value by 1)
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| === CHR Select 6 ($E000 + $E001) ===
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| $E000 $E001
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| 7 bit 0 7 bit 0
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| --------- ---------
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| .... LLLL .... HHHH
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| |||| ||||
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| |||| ++++- High 4-bits of 1 KB CHR bank at PPU $1800
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| ++++-------------- Low 4-bits
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| Note: On VRC2a, the low bit is ignored (right shift value by 1)
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| === CHR Select 7 ($E002 + $E003) ===
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| $E002 $E003
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| 7 bit 0 7 bit 0
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| --------- ---------
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| .... LLLL .... HHHH
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| |||| ||||
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| |||| ++++- High 4-bits of 1 KB CHR bank at PPU $1C00
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| ++++-------------- Low 4-bits
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| Note: On VRC2a, the low bit is ignored (right shift value by 1)
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