VRC6: Difference between revisions

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m (→‎Registers: don't imply more prg banking bits exist than do)
m (same denser and less repetitive format that's hopefully no less clear as on Namco 106)
Line 46: Line 46:
                           2: one-screen, lower bank; 3: one-screen, upper bank;)
                           2: one-screen, lower bank; 3: one-screen, upper bank;)


=== CHR Select 0 ($D000) ===
=== CHR Select 0…7 ($Dxxx, $Exxx) ===
 
{| class="wikitable"
7  bit  0
! Write to CPU address !! 1KB CHR bank affected
---------
|-
CCCC CCCC
| $D000 || $0000-$03FF
|||| ||||
|-
++++-++++- Select 1 KB CHR ROM at PPU $0000
| $D001 || $0400-$07FF
 
|-
 
| $D002 || $0800-$0BFF
=== CHR Select 1 ($D001) ===
|-
 
| $D003 || $0C00-$0FFF
7  bit  0
|-
---------
| $E000 || $1000-$13FF
CCCC CCCC
|-
|||| ||||
| $E001 || $1400-$17FF
++++-++++- Select 1 KB CHR ROM at PPU $0400
|-
 
| $E002 || $1800-$1BFF
=== CHR Select 2 ($D002) ===
|-
 
| $E003 || $1C00-$1FFF
7  bit  0
|}
---------
CCCC CCCC
|||| ||||
++++-++++- Select 1 KB CHR ROM at PPU $0800
 
=== CHR Select 3 ($D003) ===
 
7  bit  0
---------
CCCC CCCC
|||| ||||
++++-++++- Select 1 KB CHR ROM at PPU $0C00
 
=== CHR Select 4 ($E000) ===
 
7  bit  0
---------
CCCC CCCC
|||| ||||
++++-++++- Select 1 KB CHR ROM at PPU $1000
 
 
=== CHR Select 5 ($E001) ===
 
7  bit  0
---------
CCCC CCCC
|||| ||||
++++-++++- Select 1 KB CHR ROM at PPU $1400
 
=== CHR Select 6 ($E002) ===
 
7  bit  0
---------
CCCC CCCC
|||| ||||
++++-++++- Select 1 KB CHR ROM at PPU $1800
 
=== CHR Select 7 ($E003) ===
 
7  bit  0
---------
CCCC CCCC
|||| ||||
++++-++++- Select 1 KB CHR ROM at PPU $1C00
 


=== IRQ control ($F00x) ===
=== IRQ control ($F00x) ===

Revision as of 03:44, 3 January 2013

The Konami's VRC6 ASIC mapper comes in two variants. The register descriptions given here are as they exist in Akumajou Densetsu (iNES mapper 024). The A0 and A1 lines are switched in Madara and Esper Dream 2 (iNES mapper 026), so for those games, adjustments will need to be made ($x001 becomes $x002 and vice versa).



Overview

  • PRG ROM size: Up to 256 KB
  • PRG ROM bank size: 16 KB at $8000, 8 KB at $C000
  • PRG RAM: Up to 8 KB
  • CHR capacity: Up to 256 KB ROM
  • CHR bank size: 1 KB
  • Nametable mirroring: Controlled by mapper
  • Subject to bus conflicts: No

See VRC6 pinout for chip pinout.

Registers

Only address lines 0, 1, and 12-15 are used for registers, therefore mirrors can be found by ANDing the address with $F003 ($DE6A mirrors $D002)

16k PRG Select ($8000-$8003)

7  bit  0
---------
.... PPPP
     ||||
     ++++- Select 16 KB PRG ROM at $8000

8k PRG Select ($C000-$C003)

7  bit  0
---------
...P PPPP
   | ||||
   +-++++- Select 8 KB PRG ROM at $C000

Mirroring Control ($B003)

7  bit  0
---------
.... MM..
     ||
     ++--- Mirroring (0: vertical; 1: horizontal;
                          2: one-screen, lower bank; 3: one-screen, upper bank;)

CHR Select 0…7 ($Dxxx, $Exxx)

Write to CPU address 1KB CHR bank affected
$D000 $0000-$03FF
$D001 $0400-$07FF
$D002 $0800-$0BFF
$D003 $0C00-$0FFF
$E000 $1000-$13FF
$E001 $1400-$17FF
$E002 $1800-$1BFF
$E003 $1C00-$1FFF

IRQ control ($F00x)

$F000:  IRQ Latch
$F001:  IRQ Control
$F002:  IRQ Acknowledge

Many VRC mappers use the same IRQ system. For details on IRQ operation, see VRC IRQs.

Sound ($900x, $A00x, $B000-$B002)

For details on sound information, see VRC6 audio.

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