VRC6: Difference between revisions

From NESdev Wiki
Jump to navigationJump to search
(→‎PPU Banking Style ($B003): remove circumlocutious register description in favor of one I just added.)
Line 43: Line 43:
  W.PN MMDD
  W.PN MMDD
  | || ||||
  | || ||||
  | || ||++- PPU addressing mode; see below
  | || ||++- PPU banking mode; see below
  | || ++--- [[Mirroring]] varies by addressing mode, see below
  | || ++--- [[Mirroring]] varies by banking mode, see below
  | |+------ 1: Nametables come from CHRROM, 0: Nametables come from CIRAM
  | |+------ 1: Nametables come from CHRROM, 0: Nametables come from CIRAM
  | +------- CHR A10 is 1: subject to further rules 0: according to the latched value
  | +------- CHR A10 is 1: subject to further rules 0: according to the latched value
  +--------- PRG RAM enable
  +--------- PRG RAM enable


The VRC6 supports the use of a larger RAM to provide more nametables. However, no games used any more than the two from the Famicom's built-in CIRAM.
The VRC6 supports the use of a larger RAM to provide more nametables. However, no games used any more than the two from the Famicom's built-in CIRAM, nor ever use ROM nametables. As a result, the commercial games seen only ever write the values $20, $24, $28, $2C, $A0, $A4, $A8, and $AC to this register.
 
==== Nametable control in mode 0 ====
If the $20s bit is set, CHR A10 is connected according to the $04s and $08s bits as follows:
{| class="wikitable"
| 0 || vertical mirroring || CHR A10 = PPU A10
|-
| 4 || horizontal mirroring || CHR A10 = PPU A11
|-
| 8 || one-screen lower || CHR A10 = ground
|-
| 12 || one-screen upper || CHR A10 = vcc
|}
 
The upper address lines, regardless of whether the $20s bit is set, are filled with the values of CHR select 6 and 7. They are laid out according to the $04s bit:
{| class="wikitable"
| 0 || vertical ''layout'' || CHR A11…A17 = MULTIPLEX(PPU A11,CHRSEL[6],CHRSEL[7])
|-
| 4 || horizontal ''layout'' || CHR A11…A17 = MULTIPLEX(PPU A10,CHRSEL[6],CHRSEL[7])
|}
 
If the $20s bit is clear, CHR A10 follows the rest of the address lines.
 
==== Nametable control in mode 1 ====
The values written to CHRSEL[4…7] specify the banks used for nametables, without further modification.
 
For the 2KiB pattern table banks,
if the $20s bit is set, CHR A10 = PPU A10.
If the $20s bit is clear, CHR A10 parallels all the upper bits in CHRSEL[0…3]. It is then assumed that PPU A10 is connected to CHRROM separately.
 
The $04s and $08s bits are ignored.
 
==== Nametable control in mode 2 ====
The value written to CHRSEL[6] specifies the bank used in lieu of CIRAM $000-$3FF.
The value written to CHRSEL[7] specifies the bank used in lieu of CIRAM $400-$7FF.
 
These are then placed into the nametables according to the $04s bit, using the opposite table as mode 0:
{| class="wikitable"
| 0 || horizontal ''layout'' || CHR A10…A17 = MULTIPLEX(PPU A10,CHRSEL[6],CHRSEL[7])
|-
| 4 || vertical ''layout'' || CHR A10…A17 = MULTIPLEX(PPU A11,CHRSEL[6],CHRSEL[7])
|}
 
These are then placed into the nametables according to the $04s bit, using the same table as mode 0.
 
The $20s bit only affects the two pattern table banks, using the same rule as given for mode 1.
 
The only way to get one-screen mirroring is by writing the same value to both CHRSEL[6] and [7].
 
The $08s bit is ignored.
 
This behavior is identical to the [[iNES Mapper 068|Sunsoft 4]] mapper.
 
==== Nametable control in mode 3 ====
Mode 3 is identical to mode 2, except that the $08s and $20s bits affect the nametables:
 
If the $20s bit is clear, mode 3 is identical to mode 2.
 
If the $20s bit is set, CHR A10 is instead connected according to the $04s and $08s bits:
{| class="wikitable"
| 0 || horizontal mirroring || CHR A10 = PPU A11
|-
| 4 || vertical mirroring || CHR A10 = PPU A10
|-
| 8 || one-screen upper || CHR A10 = vcc
|-
| 12 || one-screen lower || CHR A10 = gnd
|}
This is the same as the table in mode 0, but with the $04s bit inverted.


=== CHR Select 0…7 ($Dxxx, $Exxx) ===
=== CHR Select 0…7 ($Dxxx, $Exxx) ===

Revision as of 02:28, 14 November 2013

The Konami's VRC6 ASIC mapper comes in two variants. The register descriptions given here are as they exist in Akumajou Densetsu (iNES Mapper 024). The A0 and A1 lines are switched in Madara and Esper Dream 2 (iNES Mapper 026), so for those games, adjustments will need to be made ($x001 becomes $x002 and vice versa).



Overview

  • PRG ROM size: Up to 256 KB
  • PRG ROM bank size: 16 KB at $8000, 8 KB at $C000
  • PRG RAM: Up to 8 KB
  • CHR capacity: Up to 256 KB ROM
  • CHR bank size: 1 KB
  • Nametable mirroring: Controlled by mapper
  • Subject to bus conflicts: No

See VRC6 pinout for chip pinout.

Registers

Only address lines 0, 1, and 12-15 are used for registers, therefore mirrors can be found by ANDing the address with $F003 ($DE6A mirrors $D002)

16k PRG Select ($8000-$8003)

7  bit  0
---------
.... PPPP
     ||||
     ++++- Select 16 KB PRG ROM at $8000

8k PRG Select ($C000-$C003)

7  bit  0
---------
...P PPPP
   | ||||
   +-++++- Select 8 KB PRG ROM at $C000

PPU Banking Style ($B003)

7  bit  0
---------
W.PN MMDD
| || ||||
| || ||++- PPU banking mode; see below
| || ++--- Mirroring varies by banking mode, see below
| |+------ 1: Nametables come from CHRROM, 0: Nametables come from CIRAM
| +------- CHR A10 is 1: subject to further rules 0: according to the latched value
+--------- PRG RAM enable

The VRC6 supports the use of a larger RAM to provide more nametables. However, no games used any more than the two from the Famicom's built-in CIRAM, nor ever use ROM nametables. As a result, the commercial games seen only ever write the values $20, $24, $28, $2C, $A0, $A4, $A8, and $AC to this register.

CHR Select 0…7 ($Dxxx, $Exxx)

For brevity, we refer to the $Dxxx and $Exxx registers as R0 through R7.

The lower 3 bits of the $B003 register affect where the registers are used:

[$B003] & 7 → 0 4 1 or 5 2 or 3 6 or 7
PPU bank Registers used
$0000-$03FF R0 R0 R0 R0 R0
$0400-$07FF R1 R1 R0 R1 R1
$0800-$0BFF R2 R2 R1 R2 R2
$0C00-$0FFF R3 R3 R1 R3 R3
$1000-$13FF R4 R4 R2 R4 R4
$1400-$17FF R5 R5 R2 R4 R4
$1800-$1BFF R6 R6 R3 R5 R5
$1C00-$1FFF R7 R7 R3 R5 R5
$2000-$23FF R6 R6 R4 R6 R6
$2400-$27FF R7 R6 R5 R6 R7
$2800-$2BFF R6 R7 R6 R7 R6
$2C00-$2FFF R7 R7 R7 R7 R7

For the pattern tables, when the $20s bit of $B003 is set, 2 KiB banks pass PPU A10 through (limiting the register to seven bits wide by ignoring the LSB).

For the nametables, if the $20s bit of $B003 is set and the lower 4 bits of $B003 have one of the following values, CHR A10 is replaced:

[$B003] & 15 CHR A10
0 or 7 PPU A10 ("vertical mirroring")
4 or 3 PPU A11 ("horizontal mirroring")
8 or 15 Ground
12 or 11 Vcc
all other values not replaced

If the $20s bit is clear, in both the pattern and name tables, the full eight-bit value from the register is used, even if this causes duplication. If these modes had ever been used, we assume Konami would have connected PPU A10 to the CHR ROM manually.

IRQ control ($F00x)

$F000:  IRQ Latch
$F001:  IRQ Control
$F002:  IRQ Acknowledge

Many VRC mappers use the same IRQ system. For details on IRQ operation, see VRC IRQs.

Sound ($900x, $A00x, $B000-$B002)

For details on sound information, see VRC6 audio.

Retrieved from "https://www.nesdev.org/w/index.php?title=VRC6&oldid=12465"