VRC6 audio

Overview

Konami's VRC6 mapper provided 3 extra channels for sound: two pulse waves, and one sawtooth. All channels operate similarly to the native channels in the NES APU.

On some boards, the A0 and A1 lines were switched, so for those boards, registers will need adjustment when emulating ($x001 will become $x002 and vice versa). Registers listed here are how they are for 悪魔城伝説 (Akumajou Densetsu, iNES mapper 024). For Madara and Esper Dream 2 (iNES mapper 026), you will need to adjust the registers.

Registers

Pulse Control ($9000,$A000)

$9000 controls Pulse 1

$A000 controls Pulse 2

7  bit  0
---- ----
MDDD VVVV
|||| ||||
|||| ++++- Volume
|+++------ Duty Cycle
+--------- Mode

Pulse Freq Low ($9001,$A001)

$9001 controls Pulse 1

$A001 controls Pulse 2

7  bit  0
---- ----
FFFF FFFF
|||| ||||
++++-++++- Low 8 bits of frequency

Pulse Freq High ($9002,$A002)

$9002 controls Pulse 1

$A002 controls Pulse 2

7  bit  0
---- ----
E... FFFF
|    ||||
|    ++++- High 4 bits of frequency
+--------- Enable (0 = channel disabled)

Saw Accum Rate ($B000)

7  bit  0
---- ----
..AA AAAA
  ++-++++- Accumulator Rate (controls volume)

Saw Freq Low ($B001)

7  bit  0
---- ----
FFFF FFFF
|||| ||||
++++-++++- Low 8 bits of frequency

Saw Freq High ($B002)

7  bit  0
---- ----
E... FFFF
|    ||||
|    ++++- High 4 bits of frequency
+--------- Enable (0 = channel disabled)

Pulse Channels

The VRC6 pulse channels operate similarly to the NES's own pulse channels. The CPU clock rate (1.79 MHz) drives the 12-bit divider 'F'. Every cycle the divider counts down until it reaches zero, at which point the divider resets and the duty cycle generator is clocked.

The duty cycle generator takes 16 steps. When the current step is less than or equal to the given duty cycle 'D', the current channel volume 'V' is output. Otherwise, 0 is output. Therefore, 'D' values provide the following duty cycles:

D=0 - 1/16  (6.25%)
D=1 - 2/16  (12.5%)
D=2 - 3/16  (18.75%)
D=3 - 4/16  (25%)
D=4 - 5/16  (31.25%)
D=5 - 6/16  (37.5%)
D=6 - 7/16  (43.75%)
D=7 - 8/16  (50%)

When the mode bit 'M' is set, the channel enters digitized mode. In this mode the duty cycle generator is ignored and the current volume is output regardless of the current duty.

When the channel is disabled by clearing the 'E' bit, output is forced to 0.

Sawtooth Channel

For the sawtooth, the CPU clock rate drives a 12-bit divider 'F'. Every cycle, the divider counts down until it reaches zero, at which point it reloads and clocks the accumulator. However, it seems that the accumulator only reacts on every 2 clocks.

When clocked, the rate value 'A' is added to an internal 8-bit accumulator. The high 5 bits of the accumulator are then output (provided the channel is enabled by having the 'E' bit set). After 'A' has been added 6 times, on the 7th clock, instead of 'A' being added, the internal accumulator is reset to zero.

For an example, assume an 'A' value of $08

Step     Accumulator    Output
------------------------------
 0          $00          $00
 1          $00          $00  (odd step, do nothing)
 2          $08          $01  (even step, add 'A' to accumulator)
 3          $08          $01
 4          $10          $02
 5          $10          $02
 6          $18          $03
 7          $18          $03
 8          $20          $04
 9          $20          $04
10          $28          $05
11          $28          $05
12          $30          $06
13          $30          $06
 0          $00          $00  (14th step, reset accumulator)
 1          $00          $00
 2          $08          $01
...

If 'A' is too high, the accumulator will wrap, resulting in distorted sound.

References

• VRCVI Chip Info by Kevin Horton