VRC7 pinout: Difference between revisions

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m (Created page with '<pre> Legend: ------- (s) means this pin connects to the System (r) this only connects to the ROM (w) this is a SRAM/WRAM connection only PRG : these connect to the PRG ROM and/...')
 
m (These are functional overlays, the original functionality isn't disabled)
 
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<pre>
Konami [[VRC7]]: 48-pin 0.6" PDIP marked: "VRC VII 053982" (canonically '''iNES Mapper 085''')
Legend:
                  .---\/---.
-------
(PPU /RD) OR A -> | 01  48 | -> OR Y (NC)
(PPU A13) OR B -> | 02  47 | <- M2
            GND -- | 03  46 | -> WRAM /CS
            R/W -> | 04  45 | <- /ROMSEL
          /IRQ <+ | 05  44 | -> PRG /CS
      CIRAM A10 <- | 06  43 | -> Audio Out
        CPU D0 <> | 07  42 | -- +5V
        CPU D1 <> | 08  41 | -> CHR A17
        CPU D2 <> | 09  40 | -> CHR A16
        CPU D3 <> | 10  39 | -> CHR A15
        CPU D4 <> | 11  38 | -> CHR A14
        CPU D5 <> | 12  37 | -> CHR A13
        CPU D6 <> | 13  36 | -> CHR A12
        CPU D7 <> | 14  35 | -> CHR A11
        /DEBUG -> | 15  34 | -> CHR A10
        CPU A5 -> | 16  33 | <- PPU A12
    Crystal X2 -> | 17  32 | <- PPU A11
    Crystal X1 <- | 18  31 | <- PPU A10
        CPU An -> | 19  30 | -- +5V
        PRG A13 <- | 20  29 | <- CPU A14
        PRG A14 <- | 21  28 | <- CPU A13
        PRG A15 <- | 22  27 | <- CPU A12
        PRG A16 <- | 23  26 | -> PRG A18
            GND -- | 24  25 | -> PRG A17
                  `--------'
 
  01,02: The OR gate on pins 1, 2, and 48 was intended for a 28-pin
          128KiB CHR ROM, but TTA2 doesn't use it. Perhaps it's too slow?
          This can be considered a general-purpose OR gate when not in debug mode.
  17,18: missing on TTA2, 3.58MHz [[wikipedia:Ceramic resonator|ceramic resonator]] on LP
          Note: LP uses a 3-pin resonator, presumably with built-in loading caps.
          An equivalent 2-pin quartz resonator will require loading caps approx. 18pF.
                          _
                        || || 3.579545 MHz
          (VRC7.17) --+--|| ||--+-- (VRC7.18)
                      |  ||_||  |
                    ---      ---
                18pF ---      --- 18pF
                      |        |
                      +----+----+
                          |
                          GND
          (Your resonator's datasheet may make a suggestion for this value.)
  19: A3 on TTA2, A4 on LP
Expansion audio mixing circuit:[//forums.nesdev.org/viewtopic.php?p=41523#p41523]
    The audio is mixed through a ceramic daughterboard with a 9 pin SIP connector. Pins 4-6 are unconnected,
    since they were primarily used for laser trimming the resistors during production.
            From 2A03---o--+-----------+
            (Cart.45)      |          |
            To RF-------o--|          |
            (Cart.46)      |          |
            GND---------o--|          |
                          |          |
            NC          o--|          |
            (Mix.4)        |          |
            NC          o--|          |
            (Mix.5)        |          |
            NC          o--|          |
            (Mix.6)        |          |
            GND---------o--|          |
                          |          |
            From VRC7---o--|          |
            (VRC7.43)      |          |
            VCC---------o--+-----------+
 
Equivalent circuit schematic:
    The daughterboard uses a dual op-amp for amplification. Only one amplifier is used.
            From 2A03----------------------------------------------------/\/\/---+
            (Cart.45)                                          _        3.9K    |
                                                              | \                |
            From VRC7---+---/\/\/---+--------+----------------|+  \              |
            (VRC7.43)  /  27K    |        /                |IC.A>-+---/\/\/---+---To RF
                        \          ---      \            +--|-  /  |  2.2K        (Cart.46)
                        / 2.2K    --- 4.7n  / 33K        |  |_/    |
                        |          |        |            |  240K  |
                        +-----------+--------+    NC------+--/\/\/--+
                        |                          (Mix.5) /        |
                        | VCC---+-------+                  \        |
                        |  |  _ |      |                  / 4.3K    |
                        |  | | \|      |          NC------+        +---NC
                        |  +-|+  \    ---        (Mix.6) |        /  (Mix.4)
                        |  | |IC.B>--x --- 0.1u          ---        \
                        |  +-|-  /      |                --- 0.22u  / 910
                        |    |_/|      |                  |        |
            GND---------+-------+-------+------------------+---------+


(s) means this pin connects to the System
When the DEBUG pin is tied low, several pins gain function:
(r) this only connects to the ROM
                  .---\/---.
(w) this is a SRAM/WRAM connection only
(PPU /RD) OR A -> | 01  48 | -> OR Y (NC)
PRG : these connect to the PRG ROM and/or fami's PRG pins
          '''A(w)''' -> | 02  47 | <- '''A(y)'''
WRAM : this hooks to the WRAM
            GND -- | 03  46 | -> WRAM /CS
          '''A(x)''' -> | 04  45 | <- /ROMSEL
          /IRQ <+ | 05  44 | -> PRG /CS
                  :       :
        PRG A13 <- | 20  29 | <- CPU A14
        PRG A14 <- | 21  28 | <- '''A(z)'''
        PRG A15 <- | 22  27 | <- '''/IC'''
        PRG A16 <- | 23  26 | -> PRG A18
            GND -- | 24  25 | -> PRG A17
                  `--------'
For more information on debug mode, see [[VRC7_audio#Debug_Mode|VRC7 audio: Debug Mode]]


Note: There is a 3.58Mhz ceramic resonator connected to the "X1" and "X2"
pins.  it is the three-pin style with internal caps tied to the third pin
which is grounded.
                                 
Chip is physically marked: "VRV VII 053982"


                                  .----\/----.
See also:
            *1 (RAM&s) CHR /OE - |01      48| - NC
* Decap'ed VRC7: https://siliconpr0n.org/archive/doku.php?id=digshadow:konami:vrc_vii_053982
            *1 (RAM&s) CHR /CE - |02      47| - M2 (s)
* Quietust's annotations for the above decap: https://www.qmtpro.com/~nes/chipimages/#vrc7
                            GND - |03      46| - /CE WRAM (w)
* More commentary on VRC7 DEBUG mode: https://siliconpr0n.org/archive/doku.php?id=vendor:yamaha:opl2#vrc7_debug_mode
                        (s) R/W - |04      45| - PRG /A15 (s) (aka /CE)
                      (s) /IRQ - |05      44| - PRG ROM /CE (r)
                  (s) CIRAM A11 - |06      43| - Audio Out
                        (s) PD0 - |07      42| - +5V
                        (s) PD1 - |08      41| - NC
                        (s) PD2 - |09      40| - NC
                        (s) PD3 - |10      39| - NC
                        (s) PD4 - |11      38| - NC
                        (s) PD5 - |12      37| - NC
                        (s) PD6 - |13      36| - CHR RAM A12
                        (s) PD7 - |14      35| - CHR RAM A11
                            +5V - |15      34| - CHR RAM A10
                    (s) PRG A5 - |16      33| - CHR A12 (s)
                    Crystal X2 - |17      32| - CHR A11 (s)
                    Crystal X1 - |18      31| - CHR A10 (s)
                    (s) PRG A4 - |19      30| - +5V
                (r) PRG ROM A13 - |20      29| - PRG A14 (s)
                (r) PRG ROM A14 - |21      28| - PRG A13 (s)
                (r) PRG ROM A15 - |22      27| - PRG A12 (s)
                (r) PRG ROM A16 - |23      26| - PRG ROM A18 (r)
                            GND - |24      25| - PRG ROM A17 (r)
                                  |          |
                                  `----------'


</pre>
 
[[Category:Pinouts]]

Latest revision as of 02:16, 28 July 2022

Konami VRC7: 48-pin 0.6" PDIP marked: "VRC VII 053982" (canonically iNES Mapper 085) 

                  .---\/---.
(PPU /RD) OR A -> | 01  48 | -> OR Y (NC)
(PPU A13) OR B -> | 02  47 | <- M2
           GND -- | 03  46 | -> WRAM /CS
           R/W -> | 04  45 | <- /ROMSEL
          /IRQ <+ | 05  44 | -> PRG /CS
     CIRAM A10 <- | 06  43 | -> Audio Out
        CPU D0 <> | 07  42 | -- +5V
        CPU D1 <> | 08  41 | -> CHR A17
        CPU D2 <> | 09  40 | -> CHR A16
        CPU D3 <> | 10  39 | -> CHR A15
        CPU D4 <> | 11  38 | -> CHR A14
        CPU D5 <> | 12  37 | -> CHR A13
        CPU D6 <> | 13  36 | -> CHR A12
        CPU D7 <> | 14  35 | -> CHR A11
        /DEBUG -> | 15  34 | -> CHR A10
        CPU A5 -> | 16  33 | <- PPU A12
    Crystal X2 -> | 17  32 | <- PPU A11
    Crystal X1 <- | 18  31 | <- PPU A10
        CPU An -> | 19  30 | -- +5V
       PRG A13 <- | 20  29 | <- CPU A14
       PRG A14 <- | 21  28 | <- CPU A13
       PRG A15 <- | 22  27 | <- CPU A12
       PRG A16 <- | 23  26 | -> PRG A18
           GND -- | 24  25 | -> PRG A17
                  `--------'
 
 01,02: The OR gate on pins 1, 2, and 48 was intended for a 28-pin 
         128KiB CHR ROM, but TTA2 doesn't use it. Perhaps it's too slow?
         This can be considered a general-purpose OR gate when not in debug mode.
 17,18: missing on TTA2, 3.58MHz ceramic resonator on LP
         Note: LP uses a 3-pin resonator, presumably with built-in loading caps.
         An equivalent 2-pin quartz resonator will require loading caps approx. 18pF.
                          _
                        || || 3.579545 MHz
         (VRC7.17) --+--|| ||--+-- (VRC7.18)
                     |  ||_||  |
                    ---       ---
               18pF ---       --- 18pF
                     |         |
                     +----+----+
                          |
                         GND
         (Your resonator's datasheet may make a suggestion for this value.)
 19: A3 on TTA2, A4 on LP

Expansion audio mixing circuit:[1]
   The audio is mixed through a ceramic daughterboard with a 9 pin SIP connector. Pins 4-6 are unconnected,
    since they were primarily used for laser trimming the resistors during production.

           From 2A03---o--+-----------+
           (Cart.45)      |           |
           To RF-------o--|           |
           (Cart.46)      |           |
           GND---------o--|           |
                          |           |
           NC          o--|           |
           (Mix.4)        |           |
           NC          o--|           |
           (Mix.5)        |           |
           NC          o--|           |
           (Mix.6)        |           |
           GND---------o--|           |
                          |           |
           From VRC7---o--|           |
           (VRC7.43)      |           |
           VCC---------o--+-----------+
 
Equivalent circuit schematic:
   The daughterboard uses a dual op-amp for amplification. Only one amplifier is used.

           From 2A03----------------------------------------------------/\/\/---+
           (Cart.45)                                          _         3.9K    |
                                                             | \                |
           From VRC7---+---/\/\/---+--------+----------------|+  \              |
           (VRC7.43)   /   27K     |        /                |IC.A>-+---/\/\/---+---To RF
                       \          ---       \             +--|-  /  |   2.2K        (Cart.46)
                       / 2.2K     --- 4.7n  / 33K         |  |_/    |
                       |           |        |             |  240K   |
                       +-----------+--------+     NC------+--/\/\/--+
                       |                          (Mix.5) /         |
                       | VCC---+-------+                  \         |
                       |  |  _ |       |                  / 4.3K    |
                       |  | | \|       |          NC------+         +---NC
                       |  +-|+  \     ---         (Mix.6) |         /   (Mix.4)
                       |  | |IC.B>--x --- 0.1u           ---        \
                       |  +-|-  /      |                 --- 0.22u  / 910
                       |    |_/|       |                  |         |
           GND---------+-------+-------+------------------+---------+

When the DEBUG pin is tied low, several pins gain function: 

                  .---\/---.
(PPU /RD) OR A -> | 01  48 | -> OR Y (NC)
          A(w) -> | 02  47 | <- A(y)
           GND -- | 03  46 | -> WRAM /CS
          A(x) -> | 04  45 | <- /ROMSEL
          /IRQ <+ | 05  44 | -> PRG /CS
                  :        :
       PRG A13 <- | 20  29 | <- CPU A14
       PRG A14 <- | 21  28 | <- A(z)
       PRG A15 <- | 22  27 | <- /IC
       PRG A16 <- | 23  26 | -> PRG A18
           GND -- | 24  25 | -> PRG A17
                  `--------'

For more information on debug mode, see VRC7 audio: Debug Mode


See also:

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