MMC2

The Nintendo MMC2 is an ASIC mapper, used on the PxROM Nintendo Game Pak boards. The iNES format assigns mapper 9 to PxROM. This chip appeared in November 1987.

Overview

• PRG ROM size: 128 KB
• PRG ROM bank size: 8 KB
• PRG RAM: none
• CHR capacity: 128 KB
• CHR bank size: 4 KB
• Nametable mirroring: Vertical or horizontal, controlled by program
• Subject to bus conflicts: No

Banks

• CPU $8000-$9FFF: 8 KB switchable PRG ROM bank
• CPU $A000-$FFFF: Three 8 KB PRG ROM banks, fixed to the last three banks
• PPU $0000-$0FFF: Two 4 KB switchable CHR ROM banks
• PPU $1000-$1FFF: Two 4 KB switchable CHR ROM banks

When the PPU reads from specific tiles in the pattern table during rendering, the MMC2 sets a latch that tells it to use a different 4 KB bank number. This has the effect of setting a different bank for all tiles to the right of a given tile.

• PPU reads $0FD0 through $0FDF: latch 0 is set to $FD for subsequent reads
• PPU reads $0FE0 through $0FEF: latch 0 is set to $FE for subsequent reads
• PPU reads $1FD0 through $1FDF: latch 1 is set to $FD for subsequent reads
• PPU reads $1FE0 through $1FEF: latch 1 is set to $FE for subsequent reads

Contrary to popular belief, the MMC2 does implement this latch behaviour on both CHR ROM banks (rather than only with PPU $1000-$1FFF).

Note that the latch is switched right after both pattern table bytes are fetched, so the tiles $fd and $fe are always entierly fetched from the old latch, then a new latch value is set. Also since the PPU fetches 34 background tiles per scanline (and only 33 at most are drawn), it is possible to rely on fetches of tiles that won't show up on the screen to set latches to a known value on the next scanline. If you use vertical mirroring it's possible without affecting the image on the screen if used cleverly.

Registers

PRG ROM bank select ($A000-$AFFF)

7  bit  0
---- ----
xxxx PPPP
     ||||
     ++++- Select 8 KB PRG ROM bank for CPU $8000-$9FFF

CHR ROM $FD/0000 bank select ($B000-$BFFF)

7  bit  0
---- ----
xxxC CCCC
   | ||||
   +-++++- Select 4 KB CHR ROM bank for PPU $0000-$0FFF
           used when latch 0 = $FD

CHR ROM $FE/0000 bank select ($C000-$CFFF)

7  bit  0
---- ----
xxxC CCCC
   | ||||
   +-++++- Select 4 KB CHR ROM bank for PPU $0000-$0FFF
           used when latch 0 = $FE

CHR ROM $FD/1000 bank select ($D000-$DFFF)

7  bit  0
---- ----
xxxC CCCC
   | ||||
   +-++++- Select 4 KB CHR ROM bank for PPU $1000-$1FFF
           used when latch 1 = $FD

CHR ROM $FE/1000 bank select ($E000-$EFFF)

7  bit  0
---- ----
xxxC CCCC
   | ||||
   +-++++- Select 4 KB CHR ROM bank for PPU $1000-$1FFF
           used when latch 1 = $FE

Mirroring ($F000-$FFFF)

7  bit  0
---- ----
xxxx xxxM
        |
        +- Select nametable mirroring (0: vertical; 1: horizontal)

Hardware

The MMC2 is implemented in a 40-pin shrink-DIP package. Only one revision is known to exist.

Variants

The Nintendo MMC4, used in the FxROM board set, is a similar mapper with 16 KB switchable PRG ROM banks, a 16 KB fixed PRG ROM bank, and up to 8 KB of PRG RAM.