PPU memory map: Difference between revisions

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(Included address range.)
(→‎Programmer memory map: no line uses more than one flag)
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=== Programmer memory map ===
=== Programmer memory map ===
{| class="tabular"
{| class="tabular"
! Address || Size || Flags || Description
! Address || Size || Note || Description
|-
|-
| $0000 || $1000 || C---- || Pattern Table #0
| $0000 || $1000 || C || Pattern Table #0
|-
|-
| $1000 || $1000 || C---- || Pattern Table #1
| $1000 || $1000 || C || Pattern Table #1
|-
|-
| $2000  ||$03C0 || ----- || Name Table #0
| $2000  ||$03C0 || || Name Table #0
|-
|-
| $23C0  ||$0040 || ----- || Attribute Table #0
| $23C0  ||$0040 || || Attribute Table #0
|-
|-
| $2400  ||$03C0 || -N--- || Name Table #1
| $2400  ||$03C0 || N || Name Table #1
|-
|-
| $27C0  ||$0040 || -N--- || Attribute Table #1
| $27C0  ||$0040 || N || Attribute Table #1
|-
|-
| $2800  ||$03C0 || -N--- || Name Table #2
| $2800  ||$03C0 || N || Name Table #2
|-
|-
| $2BC0  ||$0040 || -N--- || Attribute Table #2
| $2BC0  ||$0040 || N || Attribute Table #2
|-
|-
| $2C00  ||$03C0 || -N--- || Name Table #3
| $2C00  ||$03C0 || N || Name Table #3
|-
|-
| $2FC0  ||$0040 || -N--- || Attribute Table #3
| $2FC0  ||$0040 || N || Attribute Table #3
|-
|-
| $3000  ||$0F00 || --R-- ||  
| $3000  ||$0F00 || R ||  
|-
|-
| $3F00  ||$0010 || ----- || Image palette #1
| $3F00  ||$0010 || || Image palette #1
|-
|-
| $3F10  ||$0010 || ----- || Sprite palette #1
| $3F10  ||$0010 || || Sprite palette #1
|-
|-
| $3F20  ||$00E0 || ---P- ||  
| $3F20  ||$00E0 || P ||  
|-
|-
| $4000  ||$C000 || ---F- ||  
| $4000  ||$C000 || F ||  
|}
|}




* C = Possibly CHR-ROM
* C = Either CHR ROM or CHR RAM depending on the board
* N = Mirrored (read below)
* N = Mirrored nametables (see [[Mirroring]])
* P = Palette mirror
* P = Palette mirror
* R = Mirror of $2000-2EFF (N)
* R = Mirror of $2000-2EFF (N)

Revision as of 01:07, 3 April 2010

RAM memory map

Address range Size Description
$0000-$0FFF $1000 Pattern Table 0 [lower CHR RAM bank]
$1000-$1FFF $1000 Pattern Table 1 [upper CHR RAM bank]
$2000-$2FFF $0F00 Name Tables [4 banks of $400 bytes]
$3000-$3EFF $0F00 Mirrors of Name Tables
$3F00-$3F1F $0020 Palette RAM indexes [no RGB]
$3F20-$3FFF $0080 Mirrors of palette


Programmer memory map

Address Size Note Description
$0000 $1000 C Pattern Table #0
$1000 $1000 C Pattern Table #1
$2000 $03C0 Name Table #0
$23C0 $0040 Attribute Table #0
$2400 $03C0 N Name Table #1
$27C0 $0040 N Attribute Table #1
$2800 $03C0 N Name Table #2
$2BC0 $0040 N Attribute Table #2
$2C00 $03C0 N Name Table #3
$2FC0 $0040 N Attribute Table #3
$3000 $0F00 R
$3F00 $0010 Image palette #1
$3F10 $0010 Sprite palette #1
$3F20 $00E0 P
$4000 $C000 F


  • C = Either CHR ROM or CHR RAM depending on the board
  • N = Mirrored nametables (see Mirroring)
  • P = Palette mirror
  • R = Mirror of $2000-2EFF (N)
  • F = Mirror of $0000-3FFF

Note: First draft of the PPU memory map. Taken nesdoc format as example