Taito X1-017: Difference between revisions

Revision as of 11:56, 10 October 2012

iNES Mapper 082 represents boards using Taito's X1-017 mapper IC, which provides something a little more sophisticated than MMC3. It loses the indirect addressing, adds a 3rd 8 KiB ROM slice, and has 5 KiB of battery-backed RAM.

The cartridge connector's /IRQ line is connected to the mapper IC, but it is not known how to trigger one.

Overview

PRG ROM size: 256 KiB (maybe 512 KiB?)
PRG ROM bank size: 8 KiB
PRG RAM: Yes, internal, battery backed.
CHR capacity: 256 KiB ROM
CHR bank size: 1 KiB and 2 KiB
Nametable mirroring: Controlled by mapper
Subject to bus conflicts: no

Banks

CPU $6000-$73FF: 5 KiB PRG RAM divided into 3 protection regions
CPU $7EF0-$7EFF: Mapper registers
CPU $8000-$9FFF: 8 KB switchable PRG ROM bank
CPU $A000-$BFFF: 8 KB switchable PRG ROM bank
CPU $C000-$DFFF: 8 KB switchable PRG ROM bank
CPU $E000-$FFFF: 8 KB PRG ROM bank, fixed to the last bank
PPU $0000-$07FF (or $1000-$17FF): 2 KB switchable CHR bank
PPU $0800-$0FFF (or $1800-$1FFF): 2 KB switchable CHR bank
PPU $1000-$13FF (or $0000-$03FF): 1 KB switchable CHR bank
PPU $1400-$17FF (or $0400-$07FF): 1 KB switchable CHR bank
PPU $1800-$1BFF (or $0800-$0BFF): 1 KB switchable CHR bank
PPU $1C00-$1FFF (or $0C00-$0FFF): 1 KB switchable CHR bank

Registers

CHR Select 0 ($7EF0)

7  bit  0
CCCC CCC.
|||| |||
++++-+++-- Select 2 KiB CHR ROM at PPU $0000 or $1000

CHR Select 1 ($7EF1)

7  bit  0
CCCC CCC.
|||| |||
++++-+++-- Select 2 KiB CHR ROM at PPU $0800 or $1800

CHR Select 2 ($7EF2)

7  bit  0
CCCC CCCC
|||| ||||
++++-++++- Select 1 KiB CHR ROM at PPU $1000 or $0000

CHR Select 3 ($7EF3)

7  bit  0
CCCC CCCC
|||| ||||
++++-++++- Select 1 KiB CHR ROM at PPU $1400 or $0400

CHR Select 4 ($7EF4)

7  bit  0
CCCC CCCC
|||| ||||
++++-++++- Select 1 KiB CHR ROM at PPU $1800 or $0800

CHR Select 5 ($7EF5)

7  bit  0
CCCC CCCC
|||| ||||
++++-++++- Select 1 KiB CHR ROM at PPU $1C00 or $0C00

CHR Mode / Mirroring Control ($7EF6)

7  bit  0
.... ..CM
       ||
       |+- Mirroring (0:Horizontal, 1:Vertical)
       +-- CHR A12 inversion (0: two 2 KB banks at $0000-$0FFF,
                                 four 1 KB banks at $1000-$1FFF;
                              1: two 2 KB banks at $1000-$1FFF,
                                 four 1 KB banks at $0000-$0FFF)

PRG RAM enable 0 ($7EF7)

7  bit  0
XXXX XXXX
|||| ||||
++++-++++- Write $CA to enable RAM from $6000 to $67FF, write anything else to disable

PRG RAM enable 1 ($7EF8)

7  bit  0
XXXX XXXX
|||| ||||
++++-++++- Write $69 to enable RAM from $6800 to $6FFF, write anything else to disable

PRG RAM enable 2 ($7EF9)

7  bit  0
XXXX XXXX
|||| ||||
++++-++++- Write $84 to enable RAM from $7000 to $73FF, write anything else to disable

PRG Select 0 ($7EFA)

7  bit  0
PPPP PP..
|||| ||
++++-++--- Select 8 KiB PRG ROM at $8000

Note: remember that the low 2 bits are not used (right-shift written values by 2)

PRG Select 1 ($7EFB)

7  bit  0
PPPP PP..
|||| ||
++++-++--- Select 8 KiB PRG ROM at $A000

PRG Select 2 ($7EFC)

7  bit  0
PPPP PP..
|||| ||
++++-++--- Select 8 KiB PRG ROM at $C000

Example Games

SD Keiji - Blader
Kyuukyoku Harikiri Stadium

References

BootGod mentions the RAM protect registers: http://forums.nesdev.org/viewtopic.php?p=30165

@@ Line 14: / Line 14: @@
 == Banks ==
-* CPU $6000-$73FF: 5 KiB PRG RAM
+* CPU $6000-$73FF: 5 KiB PRG RAM divided into 3 protection regions
 <!-- what's between $7400 and $7EEF ? -->
 * CPU $7EF0-$7EFF: Mapper registers