User contributions for Quietust
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30 March 2013
- 15:5615:56, 30 March 2013 diff hist +164 N Talk:ExROM Created page with "For the solder pads, what are the actual connections established in each mode? --~~~~"
29 March 2013
- 20:3520:35, 29 March 2013 diff hist +318 Talk:PPU registers be more careful when adding comments - you reverted 2 of Rainwarrior's edits...
28 March 2013
- 03:2403:24, 28 March 2013 diff hist +353 N Talk:Reading 2007 during rendering Created page with "Summary: reading or writing $2007 during rendering will cause the VRAM address to increment by '''1 scanline''', just like it does at the beginning of HBLANK. I tracked this d..."
24 March 2013
- 23:2323:23, 24 March 2013 diff hist +174 Talk:Visual 2C02 No edit summary
- 18:2618:26, 24 March 2013 diff hist +67 Visual 2C02 No edit summary
- 18:2318:23, 24 March 2013 diff hist +37 Visual 2C02 →Tracing (section 6)
- 18:2118:21, 24 March 2013 diff hist +39 Visual 2C02 →Register access (section 2): actually, you DO get the value when you read - it's placed into the "value" column after the read finishes
- 18:1918:19, 24 March 2013 diff hist +101 m Visual 2C02 →Running (section 1)
- 18:1818:18, 24 March 2013 diff hist +679 Visual 2C02 →Running (section 1): describe states
- 18:1218:12, 24 March 2013 diff hist −2 Visual 2C02 No edit summary
- 04:0004:00, 24 March 2013 diff hist −3 PPU power up state I've traced circuitry inside the 2C02 which forces $2000, $2001, fine-X, VRAMaddr_T (but not VRAMaddr_V), and the $2007 read buffer to zero for the entire duration of the first frame
22 March 2013
- 03:3603:36, 22 March 2013 diff hist +463 PPU registers →Obscure details of OAMADDR
- 03:3003:30, 22 March 2013 diff hist +234 Talk:NES 2.0 →Vs PPUs and $2002: new section
20 March 2013
- 01:5801:58, 20 March 2013 diff hist +25 m User talk:Zzo38/Mapper 768 No edit summary
- 01:5801:58, 20 March 2013 diff hist +667 N User talk:Zzo38/Mapper 768 →Extra Data: new section
19 March 2013
- 00:0200:02, 19 March 2013 diff hist −7 Mouse No edit summary
- 00:0000:00, 19 March 2013 diff hist +6 m Mouse No edit summary
15 March 2013
- 23:4423:44, 15 March 2013 diff hist +50 PPU the palette is SRAM
- 13:1413:14, 15 March 2013 diff hist +120 Zapper misread - the standard Zapper is inverted, but the Vs. Zapper is *not* inverted\
- 12:5012:50, 15 March 2013 diff hist −1 Zapper it's inverted in the standard Zapper as well - "0: detected, 1: not detected"
14 March 2013
- 04:0704:07, 14 March 2013 diff hist +74 Zapper No edit summary
13 March 2013
- 23:5523:55, 13 March 2013 diff hist +4 m Zapper No edit summary
- 23:5423:54, 13 March 2013 diff hist +395 Zapper No edit summary
12 March 2013
- 20:5820:58, 12 March 2013 diff hist +64 m PPU sprite evaluation offset cycle numbers, confirmed in visual2c02
14 February 2013
- 14:2814:28, 14 February 2013 diff hist −6 PPU rendering →Prerender Scanline -1 or 261: only the vertical bits are reloaded there; the horizontal bits are reloaded earlier
- 14:2614:26, 14 February 2013 diff hist 0 m Talk:NTSC video No edit summary
- 14:2414:24, 14 February 2013 diff hist +286 Talk:NTSC video No edit summary
11 January 2013
- 03:4903:49, 11 January 2013 diff hist +683 Talk:The skinny on NES scrolling →Actual timing for V/T updates during rendering: new section
12 November 2012
- 02:2302:23, 12 November 2012 diff hist +138 Action 53 mapper →$80: Mode: clarification
5 November 2012
- 21:3621:36, 5 November 2012 diff hist −94 m Emulators →Under development: duplicate
1 November 2012
- 16:0816:08, 1 November 2012 diff hist +236 PPU pinout No edit summary
- 16:0416:04, 1 November 2012 diff hist +453 m PPU registers →Controller ($2000) > write
- 14:5014:50, 1 November 2012 diff hist +470 Talk:NTSC video No edit summary
29 October 2012
- 17:1717:17, 29 October 2012 diff hist +353 Talk:NTSC video No edit summary
27 October 2012
- 01:4301:43, 27 October 2012 diff hist +138 INES Mapper 100 Nintendulator uses 100 as a debug mapper - select PRG/CHR banks at will, choosing ROM or RAM (or nametables for PPU)
14 October 2012
- 17:1317:13, 14 October 2012 diff hist +5 m Talk:INES Mapper 151 No edit summary
- 17:1317:13, 14 October 2012 diff hist +180 N Talk:INES Mapper 151 Created page with "Does the VS version of this mapper have controllable mirroring, or does it use 4-screen VRAM like most (all?) VS games do? --~~~~"
11 August 2012
- 00:0100:01, 11 August 2012 diff hist +133 N MediaWiki talk:Sidebar Created page with "The "NESdev BBS" link needs to be updated - it's still pointing to parodius. --~~~~" current
3 August 2012
- 00:5200:52, 3 August 2012 diff hist 0 m Taito X1-017 fix copy/paste error?
24 June 2012
- 16:2916:29, 24 June 2012 diff hist +373 N Talk:INES Mapper 116 Created page with ""However, it seems important that the $8xxx, $9xxx, $Axxx regs be mapped to the entire $1000 region ('''unlike stock VRC2 which is supposedly strictly answering to $8000-$8003..."
22 March 2012
- 02:4002:40, 22 March 2012 diff hist −35 INES Mapper 005 my Copper Bars demo is NROM; though there is an MMC5 version, it was designed specifically to test execution of code from ExRAM but was never (to my knowledge) tested on a real MMC5
16 March 2012
- 03:2203:22, 16 March 2012 diff hist +6 m User:Quietust was expecting to see a delayered 2C02 by now - maybe later?
12 March 2012
- 17:3817:38, 12 March 2012 diff hist −78 m APU the Visual 2A03 just took existing images (produced using whatever expensive methods) and processed them by hand - the only cost was my own time, and I'd like to think it was worth it...
- 13:5613:56, 12 March 2012 diff hist +52 m APU No edit summary
9 December 2011
- 17:5417:54, 9 December 2011 diff hist +127 N Talk:Super NES Mouse Created page with "Is there any actual data in the first byte, or is it just all zeroes? --~~~~"
15 November 2011
- 01:5501:55, 15 November 2011 diff hist +8 m Emulator tests →CPU: that log is from Nintendulator, not FCEUX - I would know, since I'm the one who generated it in the first place
- 01:2301:23, 15 November 2011 diff hist +171 m Talk:APU DMC →DMC find
- 00:5500:55, 15 November 2011 diff hist −3 m Talk:APU DMC No edit summary
- 00:4500:45, 15 November 2011 diff hist +247 m Talk:APU DMC No edit summary
14 November 2011
- 22:5522:55, 14 November 2011 diff hist +2 m Talk:APU DMC No edit summary
- 22:5522:55, 14 November 2011 diff hist +893 Talk:APU DMC have you forgotten that the Visual 2A03 exists?
- 01:4501:45, 14 November 2011 diff hist −1,881 m Bandai EPROM mapper Redirected page to Bandai FCG board current
9 November 2011
- 18:5018:50, 9 November 2011 diff hist −1 m Cartridge and mappers' history people need to learn proper spelling and grammar...
- 18:5018:50, 9 November 2011 diff hist −197 m Cartridge and mappers' history formatting
22 October 2011
- 18:1418:14, 22 October 2011 diff hist +16 m Talk:CPU power up state revised from visual2a03
- 18:0518:05, 22 October 2011 diff hist +60 m Talk:CPU pinout No edit summary
18 October 2011
- 14:5114:51, 18 October 2011 diff hist +213 N File:Vramaddr.jpg VRAM address register within the PPU, with annotations for write enables and data inputs for $2000/$2005/$2006 and the two T->V signals. Everything appears to be consistent with the skinny on NES scrolling. current
17 October 2011
- 23:4223:42, 17 October 2011 diff hist +212 Talk:Power Pad No edit summary
15 October 2011
- 02:2202:22, 15 October 2011 diff hist −24 m User:Quietust Visual6502.org's depackager/delayerer has been unavailable for the past 2 months and is expected to remain unavailable until "early next year", so no visual 2C02 until then :(
11 October 2011
- 16:5216:52, 11 October 2011 diff hist 0 m Accuracy pretty sure this is supposed to be $2007...
28 September 2011
- 17:5917:59, 28 September 2011 diff hist +668 N Talk:NTSC video cursory examination of the PPU's video signal generator
16 September 2011
- 18:2818:28, 16 September 2011 diff hist +673 Talk:CPU pinout just tested pin 30 with my CopyNES, and it DOES enable extra I/O registers
14 September 2011
- 19:5819:58, 14 September 2011 diff hist +175 Talk:CPU pinout was that actually verified?
13 September 2011
- 01:4801:48, 13 September 2011 diff hist +79 m User:Quietust alternate contact
12 September 2011
- 00:5800:58, 12 September 2011 diff hist −2 m User:Quietust No edit summary
2 September 2011
- 03:2803:28, 2 September 2011 diff hist +75 m File:2a03 map.jpg No edit summary
- 03:2703:27, 2 September 2011 diff hist +142 m User:Quietust Visual 2A03 URL changed; also, 2C02 is in progress (though stalled for the past 3 weeks, waiting for the chip to be delayered)
26 August 2011
- 21:2821:28, 26 August 2011 diff hist +8 m Mirroring →4-screen VRAM: this too
- 21:2721:27, 26 August 2011 diff hist +2 m Mirroring →Single-Screen: I'm assuming this is what you meant here...
- 02:2002:20, 26 August 2011 diff hist +305 Talk:NES 2.0 No edit summary
14 July 2011
- 03:1003:10, 14 July 2011 diff hist +164 Talk:CPU pinout →M2: new section
13 July 2011
- 12:4112:41, 13 July 2011 diff hist +212 m Talk:APU Frame Counter No edit summary
- 12:3712:37, 13 July 2011 diff hist +188 m Talk:APU Frame Counter No edit summary
- 03:3603:36, 13 July 2011 diff hist −2 m APU Frame Counter No edit summary
- 03:2003:20, 13 July 2011 diff hist +256 Talk:APU Frame Counter more info
- 03:1603:16, 13 July 2011 diff hist 0 APU Frame Counter make them actually APU cycles...
- 03:1403:14, 13 July 2011 diff hist −17 APU Frame Counter it takes 2 CPU cycles (1 APU cycle) to reset, not 2 APU cycles
12 July 2011
- 19:3319:33, 12 July 2011 diff hist +453 Talk:APU Frame Counter No edit summary
- 13:0713:07, 12 July 2011 diff hist +91 Talk:APU Frame Counter No edit summary
10 July 2011
- 21:1421:14, 10 July 2011 diff hist −237 APU Frame Counter there is NO 240Hz divider - the frame counter is a 15-bit counter (LFSR) that generates triggers at each cycle count; also, subtract 3 from cycle counts because of the reload delay on $4017 write
6 July 2011
- 03:3703:37, 6 July 2011 diff hist +39 m PPU sprite evaluation explain why the sprite engine is seemingly idle during these points - it's waiting for other things to happen within the PPU
30 June 2011
- 02:1402:14, 30 June 2011 diff hist +92 m User:Quietust No edit summary
29 June 2011
- 18:5718:57, 29 June 2011 diff hist +55 m Talk:APU Frame Counter clarify
- 18:4118:41, 29 June 2011 diff hist +308 m Talk:APU Frame Counter No edit summary
15 June 2011
- 12:5812:58, 15 June 2011 diff hist −132 m Emulators duplicate
8 June 2011
- 16:4116:41, 8 June 2011 diff hist +16 m Talk:CPU power up state No edit summary
- 16:4016:40, 8 June 2011 diff hist +1,401 N Talk:CPU power up state using my previous trace of the reset line combined with the "regions" image overlay
- 02:1202:12, 8 June 2011 diff hist +63 m File:2a03 map.jpg there's now a layer image that highlights all of these regions
6 June 2011
- 03:0303:03, 6 June 2011 diff hist −2 m Talk:APU DMC No edit summary
- 03:0303:03, 6 June 2011 diff hist +336 Talk:APU DMC No edit summary
18 May 2011
- 20:4220:42, 18 May 2011 diff hist +106 m Talk:APU Sweep No edit summary
- 20:4120:41, 18 May 2011 diff hist +27 m Talk:APU Sweep the triangle channel is clocked by every M1 pulse, and the rest of the APU is clocked either by even M1 pulses or odd M1 pulses (with a vast majority being even)
- 17:1517:15, 18 May 2011 diff hist +500 Talk:APU Sweep No edit summary
- 03:4903:49, 18 May 2011 diff hist +399 Talk:APU Sweep No edit summary
16 May 2011
- 02:2202:22, 16 May 2011 diff hist −274 File:2a03 map.jpg created a chip images index page on my site
14 May 2011
- 17:1617:16, 14 May 2011 diff hist +398 Talk:APU Sweep food for thought and/or research
- 16:5616:56, 14 May 2011 diff hist +14 APU Sweep clarify
- 16:4616:46, 14 May 2011 diff hist +104 APU Sweep the problem isn't in pulse 2, but in pulse 1 - pulse 2 adds the two's complement during subtraction (as it should), but pulse 1 adds the ONE'S complement due to its carry input being hardwired
- 16:3716:37, 14 May 2011 diff hist +131 APU Pulse The duty cycle counter actually counts downward (since it's triggered by frequency counter underflow), but it's initialized to 000 rather than 111, which explains the waveform sequences
11 May 2011
- 03:1803:18, 11 May 2011 diff hist −10 File:Apu address.jpg it also overrides the noise channel's LFSR output and appears to also stop the triangle channel from being clocked; I don't know what it does to DPCM, but it's probably something similar current